From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Dayeol Lee <dayeol@berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
Date: Thu, 1 Nov 2018 16:55:23 -0700 [thread overview]
Message-ID: <20181101235525.29042-2-palmer@sifive.com> (raw)
In-Reply-To: <20181101235525.29042-1-palmer@sifive.com>
From: Dayeol Lee <dayeol@berkeley.edu>
pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR.
The default promotion rules will result in an integer here ("i*8" is integer, which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high bits of the CSR being wrong.
Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index f432f3b7594b..03abd8fe5eb7 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -325,7 +325,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
{
int i;
target_ulong cfg_val = 0;
- uint8_t val = 0;
+ target_ulong val = 0;
for (i = 0; i < sizeof(target_ulong); i++) {
val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
--
2.18.1
next prev parent reply other threads:[~2018-11-01 23:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 23:55 [Qemu-devel] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2 Palmer Dabbelt
2018-11-01 23:55 ` Palmer Dabbelt [this message]
2018-11-01 23:55 ` [Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer Palmer Dabbelt
2018-11-01 23:55 ` [Qemu-devel] [PULL 3/3] Add qemu-riscv@nongnu.org as the RISC-V list Palmer Dabbelt
2018-11-02 13:53 ` [Qemu-devel] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2 Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2018-10-30 21:22 [Qemu-devel] [PR RFC] " Palmer Dabbelt
2018-10-30 21:22 ` [Qemu-devel] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181101235525.29042-2-palmer@sifive.com \
--to=palmer@sifive.com \
--cc=dayeol@berkeley.edu \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).