From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 3/3] Add qemu-riscv@nongnu.org as the RISC-V list
Date: Thu, 1 Nov 2018 16:55:25 -0700 [thread overview]
Message-ID: <20181101235525.29042-4-palmer@sifive.com> (raw)
In-Reply-To: <20181101235525.29042-1-palmer@sifive.com>
We now have a RISC-V specific QEMU development list.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d550fd8b809c..10983bd52d64 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -244,6 +244,7 @@ M: Palmer Dabbelt <palmer@sifive.com>
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Sagar Karandikar <sagark@eecs.berkeley.edu>
M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+L: qemu-riscv@nongnu.org
S: Maintained
F: target/riscv/
F: hw/riscv/
--
2.18.1
next prev parent reply other threads:[~2018-11-01 23:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 23:55 [Qemu-devel] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2 Palmer Dabbelt
2018-11-01 23:55 ` [Qemu-devel] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Palmer Dabbelt
2018-11-01 23:55 ` [Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer Palmer Dabbelt
2018-11-01 23:55 ` Palmer Dabbelt [this message]
2018-11-02 13:53 ` [Qemu-devel] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2 Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2018-10-30 21:22 [Qemu-devel] [PR RFC] " Palmer Dabbelt
2018-10-30 21:22 ` [Qemu-devel] [PULL 3/3] Add qemu-riscv@nongnu.org as the RISC-V list Palmer Dabbelt
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