[Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

[Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

[Palmer Dabbelt]

The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e:

  tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +0000)

are available in the Git repository at:

  git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1

for you to fetch changes up to 00a014ac01feac875468d38c376f7e06f050f992:

  riscv: spike: Fix memory leak in the board init (2018-11-08 08:41:06 -0800)

----------------------------------------------------------------
A Single RISC-V Patch for 3.1-rc1

This tag contains a single patch that I'd like to target for rc1: a fix
for a memory leak that was detected by static code analysis.

There are still three patch sets that I'd like to try to get up for 3.1:

* The patch set Basian just published that contains fixes for a pair of
  issues he found when converting our port to decodetree.
* An as-of-yet-unwritten fix to the third issue that Basian pointed out.
* A fix to our fflags bug, which is currently coupled to some CSR
  refactoring that I don't think is OK for 3.1.

I'm at Plumbers next week (and I think Alistair is there too?), but I'll
try to find a way to squeeze in as much as possible.

----------------------------------------------------------------
Alistair Francis (1):
      riscv: spike: Fix memory leak in the board init

 hw/riscv/spike.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

[Qemu-devel] [PULL] riscv: spike: Fix memory leak in the board init

[Palmer Dabbelt]

From: Alistair Francis <Alistair.Francis@wdc.com>

Coverity caught a malloc() call that was never freed. This patch ensures
that we free the memory but also updates the allocation to use
g_strdup_printf() instead of malloc().

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/spike.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 8a712ed49026..268df04c3c7d 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -316,9 +316,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
 
     /* build config string with supplied memory size */
     char *isa = riscv_isa_string(&s->soc.harts[0]);
-    size_t config_string_size = strlen(config_string_tmpl) + 48;
-    char *config_string = malloc(config_string_size);
-    snprintf(config_string, config_string_size, config_string_tmpl,
+    char *config_string = g_strdup_printf(config_string_tmpl,
         (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
         (uint64_t)memmap[SPIKE_DRAM].base,
         (uint64_t)ram_size, isa,
@@ -345,6 +343,8 @@ static void spike_v1_09_1_board_init(MachineState *machine)
     /* Core Local Interruptor (timer and IPI) */
     sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
         smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
+
+    g_free(config_string);
 }
 
 static void spike_v1_09_1_machine_init(MachineClass *mc)
-- 
2.18.1

Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

[Alistair Francis]

On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e:
>
>   tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1
>
> for you to fetch changes up to 00a014ac01feac875468d38c376f7e06f050f992:
>
>   riscv: spike: Fix memory leak in the board init (2018-11-08 08:41:06 -0800)
>
> ----------------------------------------------------------------
> A Single RISC-V Patch for 3.1-rc1
>
> This tag contains a single patch that I'd like to target for rc1: a fix
> for a memory leak that was detected by static code analysis.
>
> There are still three patch sets that I'd like to try to get up for 3.1:
>
> * The patch set Basian just published that contains fixes for a pair of
>   issues he found when converting our port to decodetree.
> * An as-of-yet-unwritten fix to the third issue that Basian pointed out.
> * A fix to our fflags bug, which is currently coupled to some CSR
>   refactoring that I don't think is OK for 3.1.

There is one more patch fixing a memory leak in the virt board as well.

>
> I'm at Plumbers next week (and I think Alistair is there too?), but I'll
> try to find a way to squeeze in as much as possible.

Yep! I'll be there.

Alistair

>
> ----------------------------------------------------------------
> Alistair Francis (1):
>       riscv: spike: Fix memory leak in the board init
>
>  hw/riscv/spike.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
>

Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

[Palmer Dabbelt]

On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistair23@gmail.com wrote:
> On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e:
>>
>>   tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +0000)
>>
>> are available in the Git repository at:
>>
>>   git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1
>>
>> for you to fetch changes up to 00a014ac01feac875468d38c376f7e06f050f992:
>>
>>   riscv: spike: Fix memory leak in the board init (2018-11-08 08:41:06 -0800)
>>
>> ----------------------------------------------------------------
>> A Single RISC-V Patch for 3.1-rc1
>>
>> This tag contains a single patch that I'd like to target for rc1: a fix
>> for a memory leak that was detected by static code analysis.
>>
>> There are still three patch sets that I'd like to try to get up for 3.1:
>>
>> * The patch set Basian just published that contains fixes for a pair of
>>   issues he found when converting our port to decodetree.
>> * An as-of-yet-unwritten fix to the third issue that Basian pointed out.
>> * A fix to our fflags bug, which is currently coupled to some CSR
>>   refactoring that I don't think is OK for 3.1.
>
> There is one more patch fixing a memory leak in the virt board as well.

Oh, sorry about that -- I thought they were the same patch!

Peter: let me know if you want me to submit a new copy of this PR with both 
patches or a follow-on PR.  Sorry for the noise!

>> I'm at Plumbers next week (and I think Alistair is there too?), but I'll
>> try to find a way to squeeze in as much as possible.
>
> Yep! I'll be there.
>
> Alistair
>
>>
>> ----------------------------------------------------------------
>> Alistair Francis (1):
>>       riscv: spike: Fix memory leak in the board init
>>
>>  hw/riscv/spike.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>>

Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

[Peter Maydell]

On 8 November 2018 at 18:52, Palmer Dabbelt <palmer@sifive.com> wrote:
> On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistair23@gmail.com wrote:
>>
>> On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>>>
>>>
>>> The following changes since commit
>>> a7ce790a029bd94eb320d8c69f38900f5233997e:
>>>
>>>   tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +0000)
>>>
>>> are available in the Git repository at:
>>>
>>>   git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1
>>>
>>> for you to fetch changes up to 00a014ac01feac875468d38c376f7e06f050f992:
>>>
>>>   riscv: spike: Fix memory leak in the board init (2018-11-08 08:41:06
>>> -0800)
>>>
>>> ----------------------------------------------------------------
>>> A Single RISC-V Patch for 3.1-rc1
>>>
>>> This tag contains a single patch that I'd like to target for rc1: a fix
>>> for a memory leak that was detected by static code analysis.
>>>
>>> There are still three patch sets that I'd like to try to get up for 3.1:
>>>
>>> * The patch set Basian just published that contains fixes for a pair of
>>>   issues he found when converting our port to decodetree.
>>> * An as-of-yet-unwritten fix to the third issue that Basian pointed out.
>>> * A fix to our fflags bug, which is currently coupled to some CSR
>>>   refactoring that I don't think is OK for 3.1.
>>
>>
>> There is one more patch fixing a memory leak in the virt board as well.
>
>
> Oh, sorry about that -- I thought they were the same patch!
>
> Peter: let me know if you want me to submit a new copy of this PR with both
> patches or a follow-on PR.  Sorry for the noise!

As it happens, I'd just run this pullreq through testing overnight,
so I've pushed it to master; you can send another one with the other
patch.

thanks
-- PMM

Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1

[Palmer Dabbelt]

On Fri, 09 Nov 2018 02:53:45 PST (-0800), Peter Maydell wrote:
> On 8 November 2018 at 18:52, Palmer Dabbelt <palmer@sifive.com> wrote:
>> On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistair23@gmail.com wrote:
>>>
>>> On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>>>>
>>>>
>>>> The following changes since commit
>>>> a7ce790a029bd94eb320d8c69f38900f5233997e:
>>>>
>>>>   tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +0000)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>>   git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1
>>>>
>>>> for you to fetch changes up to 00a014ac01feac875468d38c376f7e06f050f992:
>>>>
>>>>   riscv: spike: Fix memory leak in the board init (2018-11-08 08:41:06
>>>> -0800)
>>>>
>>>> ----------------------------------------------------------------
>>>> A Single RISC-V Patch for 3.1-rc1
>>>>
>>>> This tag contains a single patch that I'd like to target for rc1: a fix
>>>> for a memory leak that was detected by static code analysis.
>>>>
>>>> There are still three patch sets that I'd like to try to get up for 3.1:
>>>>
>>>> * The patch set Basian just published that contains fixes for a pair of
>>>>   issues he found when converting our port to decodetree.
>>>> * An as-of-yet-unwritten fix to the third issue that Basian pointed out.
>>>> * A fix to our fflags bug, which is currently coupled to some CSR
>>>>   refactoring that I don't think is OK for 3.1.
>>>
>>>
>>> There is one more patch fixing a memory leak in the virt board as well.
>>
>>
>> Oh, sorry about that -- I thought they were the same patch!
>>
>> Peter: let me know if you want me to submit a new copy of this PR with both
>> patches or a follow-on PR.  Sorry for the noise!
>
> As it happens, I'd just run this pullreq through testing overnight,
> so I've pushed it to master; you can send another one with the other
> patch.

OK, works for me.  Thanks!