[Qemu-devel] [PULL 00/16] target-arm queue

[Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

v2: fix compile failure on arm hosts...

thanks
-- PMM

The following changes since commit 6db87aae61bc6ac0a8cd9bc2e05d7ebfbcfd3657:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-12 17:11:22 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181113

for you to fetch changes up to 436c0cbbeb38dd97c02fe921a7cb253a18afdd86:

  target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature (2018-11-13 10:47:59 +0000)

----------------------------------------------------------------
target/arm queue:
 * Remove no-longer-needed workaround for small SAU regions for v8M
 * Remove antique TODO comment
 * MAINTAINERS: Add an entry for the 'collie' machine
 * hw/arm/sysbus-fdt: Only call match_fn callback if the type matches
 * Fix infinite recursion in tlbi_aa64_vmalle1_write()
 * ARM KVM: fix various bugs in handling of guest debugging
 * Correctly implement handling of HCR_EL2.{VI, VF}
 * Hyp mode R14 is shared with User and System
 * Give Cortex-A15 and -A7 the EL2 feature

----------------------------------------------------------------
Alex Bennée (6):
      target/arm64: properly handle DBGVR RESS bits
      target/arm64: hold BQL when calling do_interrupt()
      target/arm64: kvm debug set target_el when passing exception to guest
      tests/guest-debug: fix scoping of failcount
      arm: use symbolic MDCR_TDE in arm_debug_target_el
      arm: fix aa64_generate_debug_exceptions to work with EL2

Eric Auger (1):
      hw/arm/sysbus-fdt: Only call match_fn callback if the type matches

Peter Maydell (7):
      target/arm: Remove workaround for small SAU regions
      target/arm: Remove antique TODO comment
      Revert "target/arm: Implement HCR.VI and VF"
      target/arm: Track the state of our irq lines from the GIC explicitly
      target/arm: Correctly implement handling of HCR_EL2.{VI, VF}
      target/arm: Hyp mode R14 is shared with User and System
      target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature

Richard Henderson (1):
      target/arm: Fix typo in tlbi_aa64_vmalle1_write

Thomas Huth (1):
      MAINTAINERS: Add an entry for the 'collie' machine

 target/arm/cpu.h                  |  44 +++++++++++------
 target/arm/internals.h            |  34 +++++++++++++
 hw/arm/sysbus-fdt.c               |  12 +++--
 target/arm/cpu.c                  |  67 ++++++++++++++++++++++++-
 target/arm/helper.c               | 101 +++++++++++++-------------------------
 target/arm/kvm32.c                |   4 +-
 target/arm/kvm64.c                |  20 +++++++-
 target/arm/machine.c              |  51 +++++++++++++++++++
 target/arm/op_helper.c            |   4 +-
 MAINTAINERS                       |   7 +++
 tests/guest-debug/test-gdbstub.py |   1 +
 11 files changed, 249 insertions(+), 96 deletions(-)

Re: [Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

On 13 November 2018 at 11:52, Peter Maydell <peter.maydell@linaro.org> wrote:
> v2: fix compile failure on arm hosts...
>
> thanks
> -- PMM
>
> The following changes since commit 6db87aae61bc6ac0a8cd9bc2e05d7ebfbcfd3657:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-12 17:11:22 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181113
>
> for you to fetch changes up to 436c0cbbeb38dd97c02fe921a7cb253a18afdd86:
>
>   target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature (2018-11-13 10:47:59 +0000)
>
> ----------------------------------------------------------------
> target/arm queue:
>  * Remove no-longer-needed workaround for small SAU regions for v8M
>  * Remove antique TODO comment
>  * MAINTAINERS: Add an entry for the 'collie' machine
>  * hw/arm/sysbus-fdt: Only call match_fn callback if the type matches
>  * Fix infinite recursion in tlbi_aa64_vmalle1_write()
>  * ARM KVM: fix various bugs in handling of guest debugging
>  * Correctly implement handling of HCR_EL2.{VI, VF}
>  * Hyp mode R14 is shared with User and System
>  * Give Cortex-A15 and -A7 the EL2 feature
>
> ----------------------------------------------------------------


Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1

for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:

  linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)

----------------------------------------------------------------
target-arm queue:
 * add MHU and dual-core support to Musca boards
 * refactor some VFP insns to be gated by ID registers
 * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
 * Implement ARMv8.2-FHM extension
 * Advertise JSCVT via HWCAP for linux-user

----------------------------------------------------------------
Peter Maydell (11):
      hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
      hw/arm/armsse: Wire up the MHUs
      target/arm/cpu: Allow init-svtor property to be set after realize
      target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
      hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
      hw/arm/iotkit-sysctl: Add SSE-200 registers
      hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
      hw/arm/armsse: Unify init-svtor and cpuwait handling
      target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
      target/arm: Gate "miscellaneous FP" insns by ID register field
      Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"

Richard Henderson (5):
      target/arm: Add helpers for FMLAL
      target/arm: Implement FMLAL and FMLSL for aarch64
      target/arm: Implement VFMAL and VFMSL for aarch32
      target/arm: Enable ARMv8.2-FHM for -cpu max
      linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT

 hw/misc/Makefile.objs           |   1 +
 include/hw/arm/armsse.h         |   3 +-
 include/hw/misc/armsse-mhu.h    |  44 ++++++
 include/hw/misc/iotkit-sysctl.h |  25 +++-
 target/arm/arm-powerctl.h       |  16 +++
 target/arm/cpu.h                |  76 +++++++++--
 target/arm/helper.h             |   9 ++
 hw/arm/armsse.c                 |  91 +++++++++----
 hw/misc/armsse-mhu.c            | 198 +++++++++++++++++++++++++++
 hw/misc/iotkit-sysctl.c         | 294 ++++++++++++++++++++++++++++++++++++++--
 linux-user/elfload.c            |   2 +
 target/arm/arm-powerctl.c       |  56 ++++++++
 target/arm/cpu.c                |  32 ++++-
 target/arm/cpu64.c              |   2 +
 target/arm/helper.c             |  27 +---
 target/arm/kvm32.c              |  23 +++-
 target/arm/kvm64.c              |   2 -
 target/arm/machine.c            |   2 +-
 target/arm/translate-a64.c      |  49 ++++++-
 target/arm/translate.c          | 180 ++++++++++++++++--------
 target/arm/vec_helper.c         | 148 ++++++++++++++++++++
 MAINTAINERS                     |   2 +
 default-configs/arm-softmmu.mak |   1 +
 hw/misc/trace-events            |   4 +
 24 files changed, 1139 insertions(+), 148 deletions(-)
 create mode 100644 include/hw/misc/armsse-mhu.h
 create mode 100644 hw/misc/armsse-mhu.c

Re: [Qemu-devel] [PULL 00/16] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190228110835.16159-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190228110835.16159-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/16] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   adf2e451f3..1387294169  master     -> master
 * [new tag]               patchew/20190228110835.16159-1-peter.maydell@linaro.org -> patchew/20190228110835.16159-1-peter.maydell@linaro.org
Switched to a new branch 'test'
7cd462af85 linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
6536b571b0 target/arm: Enable ARMv8.2-FHM for -cpu max
70f6e32c72 target/arm: Implement VFMAL and VFMSL for aarch32
a18f0eab46 target/arm: Implement FMLAL and FMLSL for aarch64
6388d5b402 target/arm: Add helpers for FMLAL
529f51ac2d Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
d427f6c5f4 target/arm: Gate "miscellaneous FP" insns by ID register field
af68a3364d target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
ed368e7cc1 hw/arm/armsse: Unify init-svtor and cpuwait handling
4d50cc7660 hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
bc9df41f99 hw/arm/iotkit-sysctl: Add SSE-200 registers
7c9c58f708 hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
f97260c638 target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
49b3caa8e4 target/arm/cpu: Allow init-svtor property to be set after realize
3bdc5052d4 hw/arm/armsse: Wire up the MHUs
d2bd880083 hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit

=== OUTPUT BEGIN ===
1/16 Checking commit d2bd88008302 (hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#55: 
new file mode 100644

total: 0 errors, 1 warnings, 271 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit 3bdc5052d4d4 (hw/arm/armsse: Wire up the MHUs)
3/16 Checking commit 49b3caa8e4b3 (target/arm/cpu: Allow init-svtor property to be set after realize)
4/16 Checking commit f97260c6386b (target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset())
5/16 Checking commit 7c9c58f708c9 (hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name)
6/16 Checking commit bc9df41f9942 (hw/arm/iotkit-sysctl: Add SSE-200 registers)
ERROR: spaces required around that '*' (ctx:VxV)
#352: FILE: hw/misc/iotkit-sysctl.c:462:
+    .subsections = (const VMStateDescription*[]) {
                                             ^

total: 1 errors, 0 warnings, 372 lines checked

Patch 6/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

7/16 Checking commit 4d50cc7660f9 (hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*)
8/16 Checking commit ed368e7cc1e3 (hw/arm/armsse: Unify init-svtor and cpuwait handling)
9/16 Checking commit af68a3364d4f (target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions)
10/16 Checking commit d427f6c5f4aa (target/arm: Gate "miscellaneous FP" insns by ID register field)
11/16 Checking commit 529f51ac2d97 (Revert "arm: Allow system registers for KVM guests to be changed by QEMU code")
WARNING: Block comments use a leading /* on a separate line
#129: FILE: target/arm/kvm32.c:387:
+    /* Note that we do not call write_cpustate_to_list()

total: 0 errors, 1 warnings, 113 lines checked

Patch 11/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/16 Checking commit 6388d5b4022e (target/arm: Add helpers for FMLAL)
13/16 Checking commit a18f0eab46b3 (target/arm: Implement FMLAL and FMLSL for aarch64)
14/16 Checking commit 70f6e32c72c8 (target/arm: Implement VFMAL and VFMSL for aarch32)
15/16 Checking commit 6536b571b00d (target/arm: Enable ARMv8.2-FHM for -cpu max)
16/16 Checking commit 7cd462af8528 (linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190228110835.16159-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

On Thu, 28 Feb 2019 at 11:08, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1
>
> for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:
>
>   linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * add MHU and dual-core support to Musca boards
>  * refactor some VFP insns to be gated by ID registers
>  * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
>  * Implement ARMv8.2-FHM extension
>  * Advertise JSCVT via HWCAP for linux-user
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM

[Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

target-arm queue for 3.1: mostly bug fixes, but the "turn on
EL2 support for Cortex-A7 and -A15" is technically enabling
of a new feature... I think this is OK since we're only at rc1,
and it's easy to revert that feature bit flip if necessary.

thanks
-- PMM


The following changes since commit 5704c36d25ee84e7129722cb0db53df9faefe943:

  Merge remote-tracking branch 'remotes/kraxel/tags/fixes-31-20181112-pull-request' into staging (2018-11-12 15:55:40 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181112

for you to fetch changes up to 1a4c1a6dbf60aebddd07753f1013ea896c06ad29:

  target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature (2018-11-12 16:52:29 +0000)

----------------------------------------------------------------
target/arm queue:
 * Remove no-longer-needed workaround for small SAU regions for v8M
 * Remove antique TODO comment
 * MAINTAINERS: Add an entry for the 'collie' machine
 * hw/arm/sysbus-fdt: Only call match_fn callback if the type matches
 * Fix infinite recursion in tlbi_aa64_vmalle1_write()
 * ARM KVM: fix various bugs in handling of guest debugging
 * Correctly implement handling of HCR_EL2.{VI, VF}
 * Hyp mode R14 is shared with User and System
 * Give Cortex-A15 and -A7 the EL2 feature

----------------------------------------------------------------
Alex Bennée (6):
      target/arm64: properly handle DBGVR RESS bits
      target/arm64: hold BQL when calling do_interrupt()
      target/arm64: kvm debug set target_el when passing exception to guest
      tests/guest-debug: fix scoping of failcount
      arm: use symbolic MDCR_TDE in arm_debug_target_el
      arm: fix aa64_generate_debug_exceptions to work with EL2

Eric Auger (1):
      hw/arm/sysbus-fdt: Only call match_fn callback if the type matches

Peter Maydell (7):
      target/arm: Remove workaround for small SAU regions
      target/arm: Remove antique TODO comment
      Revert "target/arm: Implement HCR.VI and VF"
      target/arm: Track the state of our irq lines from the GIC explicitly
      target/arm: Correctly implement handling of HCR_EL2.{VI, VF}
      target/arm: Hyp mode R14 is shared with User and System
      target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature

Richard Henderson (1):
      target/arm: Fix typo in tlbi_aa64_vmalle1_write

Thomas Huth (1):
      MAINTAINERS: Add an entry for the 'collie' machine

 target/arm/cpu.h                  |  44 +++++++++++------
 target/arm/internals.h            |  34 +++++++++++++
 hw/arm/sysbus-fdt.c               |  12 +++--
 target/arm/cpu.c                  |  66 ++++++++++++++++++++++++-
 target/arm/helper.c               | 101 +++++++++++++-------------------------
 target/arm/kvm32.c                |   4 +-
 target/arm/kvm64.c                |  20 +++++++-
 target/arm/machine.c              |  51 +++++++++++++++++++
 target/arm/op_helper.c            |   4 +-
 MAINTAINERS                       |   7 +++
 tests/guest-debug/test-gdbstub.py |   1 +
 11 files changed, 248 insertions(+), 96 deletions(-)

[Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

  Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

  tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix coverity nit in int_to_float code
 * Don't set Invalid for float-to-int(MAXINT)
 * Fix fp_status_f16 tininess before rounding
 * Add various missing insns from the v8.2-FP16 extension
 * Fix sqrt_f16 exception raising
 * sdcard: Correct CRC16 offset in sd_function_switch()
 * tcg: Optionally log FPU state in TCG -d cpu logging

----------------------------------------------------------------
Alex Bennée (5):
      fpu/softfloat: int_to_float ensure r fully initialised
      target/arm: Implement FCMP for fp16
      target/arm: Implement FCSEL for fp16
      target/arm: Implement FMOV (immediate) for fp16
      target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):
      fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
      target/arm: Fix fp_status_f16 tininess before rounding
      tcg: Optionally log FPU state in TCG -d cpu logging

Philippe Mathieu-Daudé (1):
      sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):
      target/arm: Implement FMOV (general) for fp16
      target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
      target/arm: Implement FCVT (scalar, integer) for fp16
      target/arm: Implement FCVT (scalar, fixed-point) for fp16
      target/arm: Introduce and use read_fp_hreg
      target/arm: Implement FP data-processing (2 source) for fp16
      target/arm: Implement FP data-processing (3 source) for fp16

 include/qemu/log.h         |   1 +
 target/arm/helper-a64.h    |   2 +
 target/arm/helper.h        |   6 +
 accel/tcg/cpu-exec.c       |   9 +-
 fpu/softfloat.c            |   6 +-
 hw/sd/sd.c                 |   2 +-
 target/arm/cpu.c           |   2 +
 target/arm/helper-a64.c    |  10 ++
 target/arm/helper.c        |  38 +++-
 target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
 util/log.c                 |   2 +
 11 files changed, 428 insertions(+), 71 deletions(-)

Re: [Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

On 15 May 2018 at 15:06, Peter Maydell <peter.maydell@linaro.org> wrote:
> The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
>
> are available in the Git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
>
> for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
>
>   tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Fix coverity nit in int_to_float code
>  * Don't set Invalid for float-to-int(MAXINT)
>  * Fix fp_status_f16 tininess before rounding
>  * Add various missing insns from the v8.2-FP16 extension
>  * Fix sqrt_f16 exception raising
>  * sdcard: Correct CRC16 offset in sd_function_switch()
>  * tcg: Optionally log FPU state in TCG -d cpu logging
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

target-arm queue: I wanted to send out some of the easier stuff in
my review queue, at least. I'll try to work through the meatier
review work next week...

thanks
-- PMM

The following changes since commit d9aa68855724752a5684c6acfb17d8db15cec2f8:

  Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140829-1' into staging (2014-08-29 13:08:04 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140829

for you to fetch changes up to 0614601cecc8e5d9c6c5fa606b39fe388a18583a:

  target-arm: Implement pmccfiltr_write function (2014-08-29 15:00:30 +0100)

----------------------------------------------------------------
target-arm queue:
 * support PMCCNTR in ARMv8
 * various GIC fixes and cleanups
 * Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
 * Fix regression that disabled VFP for ARMv5 CPUs
 * Update to upstream VIXL 1.5

----------------------------------------------------------------
Adam Lackorzynski (4):
      arm_gic: Fix read of GICD_ICFGR
      arm_gic: GICD_ICFGR: Write model only for pre v1 GICs
      arm_gic: Do not force PPIs to edge-triggered mode
      arm_gic: Use GIC_NR_SGIS constant

Alistair Francis (6):
      target-arm: Make the ARM PMCCNTR register 64-bit
      target-arm: Implement PMCCNTR_EL0 and related registers
      target-arm: Add arm_ccnt_enabled function
      target-arm: Implement pmccntr_sync function
      target-arm: Remove old code and replace with new functions
      target-arm: Implement pmccfiltr_write function

Joel Schopp (1):
      aarch64: raise max_cpus to 8

Peter Crosthwaite (1):
      arm: Implement PMCCNTR 32b read-modify-write

Peter Maydell (3):
      disas/libvixl: Update to upstream VIXL 1.5
      target-arm: Fix regression that disabled VFP for ARMv5 CPUs
      target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values

Sergey Fedorov (1):
      hw/intc/arm_gic: honor target mask in gic_update()

 disas/libvixl/README                  |   2 +-
 disas/libvixl/a64/assembler-a64.h     | 363 ++++++++++++++++++++++++++++++----
 disas/libvixl/a64/constants-a64.h     |  68 ++++++-
 disas/libvixl/a64/cpu-a64.h           |  27 +++
 disas/libvixl/a64/decoder-a64.cc      |  15 +-
 disas/libvixl/a64/decoder-a64.h       |   1 +
 disas/libvixl/a64/disasm-a64.cc       |  88 +++++++--
 disas/libvixl/a64/disasm-a64.h        |   2 +-
 disas/libvixl/a64/instructions-a64.cc |  25 ++-
 disas/libvixl/a64/instructions-a64.h  |  10 +
 disas/libvixl/platform.h              |   8 +-
 disas/libvixl/utils.cc                |  10 +
 disas/libvixl/utils.h                 |  32 ++-
 hw/arm/virt.c                         |   2 +-
 hw/intc/arm_gic.c                     |  17 +-
 hw/intc/arm_gic_common.c              |   2 +-
 target-arm/cpu.h                      |  27 ++-
 target-arm/cpu64.c                    |   3 +-
 target-arm/helper.c                   | 138 +++++++++----
 19 files changed, 697 insertions(+), 143 deletions(-)

Re: [Qemu-devel] [PULL 00/16] target-arm queue

[Peter Maydell]

On 29 August 2014 15:37, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue: I wanted to send out some of the easier stuff in
> my review queue, at least. I'll try to work through the meatier
> review work next week...
>
> thanks
> -- PMM
>
> The following changes since commit d9aa68855724752a5684c6acfb17d8db15cec2f8:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140829-1' into staging (2014-08-29 13:08:04 +0100)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140829
>
> for you to fetch changes up to 0614601cecc8e5d9c6c5fa606b39fe388a18583a:
>
>   target-arm: Implement pmccfiltr_write function (2014-08-29 15:00:30 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * support PMCCNTR in ARMv8
>  * various GIC fixes and cleanups
>  * Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
>  * Fix regression that disabled VFP for ARMv5 CPUs
>  * Update to upstream VIXL 1.5
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM