From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMiT4-0003ay-Kq for qemu-devel@nongnu.org; Tue, 13 Nov 2018 18:51:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMiSx-0006do-J2 for qemu-devel@nongnu.org; Tue, 13 Nov 2018 18:51:36 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:45334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMiSv-0006YW-16 for qemu-devel@nongnu.org; Tue, 13 Nov 2018 18:51:29 -0500 Received: by mail-pl1-x632.google.com with SMTP id a14so2209061plm.12 for ; Tue, 13 Nov 2018 15:51:21 -0800 (PST) Date: Tue, 13 Nov 2018 15:50:43 -0800 Message-Id: <20181113235045.14155-3-palmer@sifive.com> In-Reply-To: <20181113235045.14155-1-palmer@sifive.com> References: <20181113235045.14155-1-palmer@sifive.com> From: Palmer Dabbelt Subject: [Qemu-devel] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Bastian Koppelmann , Palmer Dabbelt From: Bastian Koppelmann Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d1471d..5359088e24bc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); break; -#if defined(TARGET_RISCV64) case OPC_RISC_FMV_X_D: /* also OPC_RISC_FCLASS_D */ switch (rm) { +#if defined(TARGET_RISCV64) case 0: /* FMV */ gen_set_gpr(rd, cpu_fpr[rs1]); break; +#endif case 1: t0 = tcg_temp_new(); gen_helper_fclass_d(t0, cpu_fpr[rs1]); @@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } break; +#if defined(TARGET_RISCV64) case OPC_RISC_FMV_D_X: t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); -- 2.18.1