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From: Palmer Dabbelt <palmer@sifive.com>
To: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 3/4] target/riscv: Fix sfence.vm/a both available in any priv version
Date: Tue, 13 Nov 2018 15:50:44 -0800	[thread overview]
Message-ID: <20181113235045.14155-4-palmer@sifive.com> (raw)
In-Reply-To: <20181113235045.14155-1-palmer@sifive.com>

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

sfence.vm has been replaced in priv v1.10 spec by sfence.vma.

Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/translate.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5359088e24bc..f44eb9c41b48 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1292,10 +1292,14 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
 #ifndef CONFIG_USER_ONLY
     /* Extract funct7 value and check whether it matches SFENCE.VMA */
     if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
-        /* sfence.vma */
-        /* TODO: handle ASID specific fences */
-        gen_helper_tlb_flush(cpu_env);
-        return;
+        if (env->priv_ver == PRIV_VERSION_1_10_0) {
+            /* sfence.vma */
+            /* TODO: handle ASID specific fences */
+            gen_helper_tlb_flush(cpu_env);
+            return;
+        } else {
+            gen_exception_illegal(ctx);
+        }
     }
 #endif
 
@@ -1342,7 +1346,11 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
             gen_helper_wfi(cpu_env);
             break;
         case 0x104: /* SFENCE.VM */
-            gen_helper_tlb_flush(cpu_env);
+            if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+                gen_helper_tlb_flush(cpu_env);
+            } else {
+                gen_exception_illegal(ctx);
+            }
             break;
 #endif
         default:
-- 
2.18.1

  parent reply	other threads:[~2018-11-13 23:51 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-13 23:50 [Qemu-devel] [PR RFC] RISC-V Patches for 3.1-rc2 Palmer Dabbelt
2018-11-13 23:50 ` [Qemu-devel] [PULL 1/4] hw/riscv/virt: Free the test device tree node name Palmer Dabbelt
2018-11-13 23:50 ` [Qemu-devel] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only Palmer Dabbelt
2018-11-13 23:50 ` Palmer Dabbelt [this message]
2018-11-13 23:50 ` [Qemu-devel] [PULL 4/4] RISC-V: Respect fences for user-only emulators Palmer Dabbelt
2018-11-14  2:32   ` Michael Clark
2018-11-14  3:06 ` [Qemu-devel] [PR RFC] RISC-V Patches for 3.1-rc2 Michael Clark
  -- strict thread matches above, loose matches on Subject: below --
2018-11-16 21:30 [Qemu-devel] [PULL] " Palmer Dabbelt
2018-11-16 21:30 ` [Qemu-devel] [PULL 3/4] target/riscv: Fix sfence.vm/a both available in any priv version Palmer Dabbelt

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