qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	Wei Huang <wei@redhat.com>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Michael Spradling <mspradli@codeaurora.org>,
	Digant Desai <digantd@codeaurora.org>,
	Aaron Lindsay <aclindsa@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v7 03/12] target/arm: Swap PMU values before/after migrations
Date: Fri, 16 Nov 2018 16:09:18 +0000	[thread overview]
Message-ID: <20181116160909.GD23658@quinoa.localdomain> (raw)
In-Reply-To: <CAFEAcA9va2QarkMFPWNMf43u_GRDoajM-=E0dwinVEgaqRgjHQ@mail.gmail.com>

On Nov 16 14:53, Peter Maydell wrote:
> On 5 November 2018 at 18:51, Aaron Lindsay <aaron@os.amperecomputing.com> wrote:
> > Because of the PMU's design, many register accesses have side effects
> > which are inter-related, meaning that the normal method of saving CP
> > registers can result in inconsistent state. These side-effects are
> > largely handled in pmu_op_start/finish functions which can be called
> > before and after the state is saved/restored. By doing this and adding
> > raw read/write functions for the affected registers, we avoid
> > migration-related inconsistencies.
> >
> > Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
> 
> > --- a/target/arm/machine.c
> > +++ b/target/arm/machine.c
> > @@ -604,6 +604,8 @@ static int cpu_pre_save(void *opaque)
> >  {
> >      ARMCPU *cpu = opaque;
> >
> > +    pmu_op_start(&cpu->env);
> > +
> >      if (kvm_enabled()) {
> >          if (!write_kvmstate_to_list(cpu)) {
> >              /* This should never fail */
> > @@ -625,6 +627,20 @@ static int cpu_pre_save(void *opaque)
> >      return 0;
> >  }
> >
> > +static int cpu_post_save(void *opaque)
> > +{
> > +    ARMCPU *cpu = opaque;
> > +    pmu_op_finish(&cpu->env);
> > +    return 0;
> > +}
> > +
> > +static int cpu_pre_load(void *opaque)
> > +{
> > +    ARMCPU *cpu = opaque;
> > +    pmu_op_start(&cpu->env);
> > +    return 0;
> > +}
> > +
> >  static int cpu_post_load(void *opaque, int version_id)
> >  {
> >      ARMCPU *cpu = opaque;
> > @@ -672,6 +688,8 @@ static int cpu_post_load(void *opaque, int version_id)
> >      hw_breakpoint_update_all(cpu);
> >      hw_watchpoint_update_all(cpu);
> >
> > +    pmu_op_finish(&cpu->env);
> > +
> >      return 0;
> >  }
> 
> This will end up calling pmu_op_start() and pmu_op_finish()
> even if the guest is running KVM and we're not using the
> TCG code. Is that what you intended?

The counters are still stored in their 'difference' format for KVM, so I
think this still makes sense. Or is there something I'm missing about
how this will interact with KVM? I'm much more familiar with TCG.

-Aaron

  reply	other threads:[~2018-11-16 16:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-05 18:51 [Qemu-devel] [PATCH v7 00/12] More fully implement ARM PMUv3 Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 01/12] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-11-16 14:42   ` Peter Maydell
2018-11-16 16:34     ` Dr. David Alan Gilbert
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 02/12] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-11-16 14:50   ` Peter Maydell
2018-11-16 15:41     ` Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 03/12] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-11-16 14:53   ` Peter Maydell
2018-11-16 16:09     ` Aaron Lindsay [this message]
2018-11-16 16:44       ` Peter Maydell
2018-11-16 21:06         ` Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 04/12] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 05/12] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 06/12] target/arm: Implement PMOVSSET Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 07/12] target/arm: Add array for supported PMU events, generate PMCEID[01] Aaron Lindsay
2018-11-16 15:06   ` Peter Maydell
2018-11-16 20:09     ` Aaron Lindsay
2018-11-05 18:51 ` [Qemu-devel] [PATCH v7 08/12] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-11-05 18:52 ` [Qemu-devel] [PATCH v7 09/12] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-11-05 18:52 ` [Qemu-devel] [PATCH v7 10/12] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-11-16 14:59   ` Peter Maydell
2018-11-05 18:52 ` [Qemu-devel] [PATCH v7 11/12] target/arm: Implement PMSWINC Aaron Lindsay
2018-11-05 18:52 ` [Qemu-devel] [PATCH v7 12/12] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-11-16 21:22   ` Aaron Lindsay
2018-11-20 14:35     ` Peter Maydell
2018-11-06  8:55 ` [Qemu-devel] [PATCH v7 00/12] More fully implement ARM PMUv3 no-reply

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181116160909.GD23658@quinoa.localdomain \
    --to=aaron@os.amperecomputing.com \
    --cc=aclindsa@gmail.com \
    --cc=alistair.francis@xilinx.com \
    --cc=crosthwaite.peter@gmail.com \
    --cc=digantd@codeaurora.org \
    --cc=mspradli@codeaurora.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=wei@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).