From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPDXz-0000Mf-74 for qemu-devel@nongnu.org; Tue, 20 Nov 2018 16:27:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gPDXr-00061Q-4V for qemu-devel@nongnu.org; Tue, 20 Nov 2018 16:26:59 -0500 From: Aaron Lindsay Date: Tue, 20 Nov 2018 21:26:40 +0000 Message-ID: <20181120212553.8480-8-aaron@os.amperecomputing.com> References: <20181120212553.8480-1-aaron@os.amperecomputing.com> In-Reply-To: <20181120212553.8480-1-aaron@os.amperecomputing.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Cc: "qemu-devel@nongnu.org" , Michael Spradling , Digant Desai , Aaron Lindsay Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 4 ++-- target/arm/helper.c | 12 ++++++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 627e5c1995..50de58e4a2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -837,8 +837,8 @@ struct ARMCPU { uint32_t id_pfr0; uint32_t id_pfr1; uint32_t id_dfr0; - uint32_t pmceid0; - uint32_t pmceid1; + uint64_t pmceid0; + uint64_t pmceid1; uint32_t id_afr0; uint32_t id_mmfr0; uint32_t id_mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 71be6fb578..75f054fe79 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5432,7 +5432,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid0 }, + .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, @@ -5440,7 +5444,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid1 }, + .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, --=20 2.19.1