[Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Alistair Francis]

V7:
 - Fix the GPEX memory mapping thanks to Bin Meng
 - Fix the interrupt mapping thanks to Logan Gunthorpe
V6:
 - Fix the interrupt issue for the GPEX device
V5:
 - Rebase
 - Include pci.mak in the default configs
V4:
 - Fix the spike device tree
 - Don't use stdvga device
V3:
 - Remove Makefile config changes
 - Connect a network adapter to the virt device
V2:
 - Use the gpex PCIe host for virt
 - Add support for SiFive U PCIe


Alistair Francis (6):
  hw/riscv/virt: Increase the number of interrupts
  hw/riscv/virt: Adjust memory layout spacing
  hw/riscv/virt: Connect the gpex PCIe
  riscv: Enable VGA and PCIE_VGA
  hw/riscv/sifive_u: Connect the Xilinx PCIe
  hw/riscv/virt: Connect a VirtIO net PCIe device

 default-configs/riscv32-softmmu.mak |  10 +-
 default-configs/riscv64-softmmu.mak |  10 +-
 hw/riscv/sifive_u.c                 |  64 +++++++++++
 hw/riscv/virt.c                     | 161 ++++++++++++++++++++++++++--
 include/hw/riscv/sifive_u.h         |   4 +-
 include/hw/riscv/virt.h             |  15 ++-
 6 files changed, 250 insertions(+), 14 deletions(-)

-- 
2.19.1

[Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Alistair Francis]

Increase the number of interrupts to match the HiFive Unleashed board.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
     UART0_IRQ = 10,
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
-    VIRTIO_NDEV = 10
+    VIRTIO_NDEV = 0x35
 };
 
 enum {
-- 
2.19.1

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Logan Gunthorpe]

On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Increase the number of interrupts to match the HiFive Unleashed board.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  include/hw/riscv/virt.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 91163d6cbf..7cb2742070 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -45,7 +45,7 @@ enum {
>      UART0_IRQ = 10,
>      VIRTIO_IRQ = 1, /* 1 to 8 */
>      VIRTIO_COUNT = 8,
> -    VIRTIO_NDEV = 10
> +    VIRTIO_NDEV = 0x35

Why 0x35? Based on the PCI patch we are using only 36 interrupts, not 53...

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Alistair Francis]

On Wed, Nov 21, 2018 at 9:58 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Increase the number of interrupts to match the HiFive Unleashed board.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  include/hw/riscv/virt.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> > index 91163d6cbf..7cb2742070 100644
> > --- a/include/hw/riscv/virt.h
> > +++ b/include/hw/riscv/virt.h
> > @@ -45,7 +45,7 @@ enum {
> >      UART0_IRQ = 10,
> >      VIRTIO_IRQ = 1, /* 1 to 8 */
> >      VIRTIO_COUNT = 8,
> > -    VIRTIO_NDEV = 10
> > +    VIRTIO_NDEV = 0x35
>
> Why 0x35? Based on the PCI patch we are using only 36 interrupts, not 53...

This is just for future proofing. There is no reason to set the number
lower then the number of interrupts we have, now hopefully this won't
keep churning every time we add a device.

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Logan Gunthorpe]

On 2018-11-21 11:17 a.m., Alistair Francis wrote:
> On Wed, Nov 21, 2018 at 9:58 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>>
>>
>>
>> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
>>> Increase the number of interrupts to match the HiFive Unleashed board.
>>>
>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>> ---
>>>  include/hw/riscv/virt.h | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
>>> index 91163d6cbf..7cb2742070 100644
>>> --- a/include/hw/riscv/virt.h
>>> +++ b/include/hw/riscv/virt.h
>>> @@ -45,7 +45,7 @@ enum {
>>>      UART0_IRQ = 10,
>>>      VIRTIO_IRQ = 1, /* 1 to 8 */
>>>      VIRTIO_COUNT = 8,
>>> -    VIRTIO_NDEV = 10
>>> +    VIRTIO_NDEV = 0x35
>>
>> Why 0x35? Based on the PCI patch we are using only 36 interrupts, not 53...
> 
> This is just for future proofing. There is no reason to set the number
> lower then the number of interrupts we have, now hopefully this won't
> keep churning every time we add a device.

Makes sense. Still 53 is an odd number.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:45 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 11:17 a.m., Alistair Francis wrote:
> > On Wed, Nov 21, 2018 at 9:58 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >>
> >>
> >>
> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> >>> Increase the number of interrupts to match the HiFive Unleashed board.
> >>>
> >>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >>> ---
> >>>  include/hw/riscv/virt.h | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> >>> index 91163d6cbf..7cb2742070 100644
> >>> --- a/include/hw/riscv/virt.h
> >>> +++ b/include/hw/riscv/virt.h
> >>> @@ -45,7 +45,7 @@ enum {
> >>>      UART0_IRQ = 10,
> >>>      VIRTIO_IRQ = 1, /* 1 to 8 */
> >>>      VIRTIO_COUNT = 8,
> >>> -    VIRTIO_NDEV = 10
> >>> +    VIRTIO_NDEV = 0x35
> >>
> >> Why 0x35? Based on the PCI patch we are using only 36 interrupts, not 53...
> >
> > This is just for future proofing. There is no reason to set the number
> > lower then the number of interrupts we have, now hopefully this won't
> > keep churning every time we add a device.
>
> Makes sense. Still 53 is an odd number.

Agreed. It's the same number as the last interrupt in the QEMU SiFive
U machine. So that is where it came from.

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Logan Gunthorpe]

On 2018-11-21 11:49 a.m., Alistair Francis wrote:
> Agreed. It's the same number as the last interrupt in the QEMU SiFive
> U machine. So that is where it came from.

Ok, can we have a comment for that?

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:56 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 11:49 a.m., Alistair Francis wrote:
> > Agreed. It's the same number as the last interrupt in the QEMU SiFive
> > U machine. So that is where it came from.
>
> Ok, can we have a comment for that?

I don't think we really need a comment. It's just a made up number. It
just has to be higher then the actual number of used interrupts. It
can be changed in the future if required.

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Logan Gunthorpe]

On 2018-11-21 11:59 a.m., Alistair Francis wrote:
> On Wed, Nov 21, 2018 at 10:56 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>>
>>
>>
>> On 2018-11-21 11:49 a.m., Alistair Francis wrote:
>>> Agreed. It's the same number as the last interrupt in the QEMU SiFive
>>> U machine. So that is where it came from.
>>
>> Ok, can we have a comment for that?
> 
> I don't think we really need a comment. It's just a made up number. It
> just has to be higher then the actual number of used interrupts. It
> can be changed in the future if required.

If it's confusing to me it'll be confusing to others reading it. At
least put something in the commit log describing the choice of number
and why it's not important...

Logan

[Qemu-devel] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing

[Alistair Francis]

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2b38f89070..6b6fa39aaa 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -47,14 +47,14 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } virt_memmap[] = {
-    [VIRT_DEBUG] =    {        0x0,      0x100 },
-    [VIRT_MROM] =     {     0x1000,    0x11000 },
-    [VIRT_TEST] =     {   0x100000,     0x1000 },
-    [VIRT_CLINT] =    {  0x2000000,    0x10000 },
-    [VIRT_PLIC] =     {  0xc000000,  0x4000000 },
-    [VIRT_UART0] =    { 0x10000000,      0x100 },
-    [VIRT_VIRTIO] =   { 0x10001000,     0x1000 },
-    [VIRT_DRAM] =     { 0x80000000,        0x0 },
+    [VIRT_DEBUG] =       {        0x0,         0x100 },
+    [VIRT_MROM] =        {     0x1000,       0x11000 },
+    [VIRT_TEST] =        {   0x100000,        0x1000 },
+    [VIRT_CLINT] =       {  0x2000000,       0x10000 },
+    [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
+    [VIRT_UART0] =       { 0x10000000,         0x100 },
+    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_DRAM] =        { 0x80000000,           0x0 },
 };
 
 static uint64_t load_kernel(const char *kernel_filename)
-- 
2.19.1

Re: [Qemu-devel] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing

[Logan Gunthorpe]

On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Logan Gunthorpe <logang@deltatee.com>

> ---
>  hw/riscv/virt.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2b38f89070..6b6fa39aaa 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -47,14 +47,14 @@ static const struct MemmapEntry {
>      hwaddr base;
>      hwaddr size;
>  } virt_memmap[] = {
> -    [VIRT_DEBUG] =    {        0x0,      0x100 },
> -    [VIRT_MROM] =     {     0x1000,    0x11000 },
> -    [VIRT_TEST] =     {   0x100000,     0x1000 },
> -    [VIRT_CLINT] =    {  0x2000000,    0x10000 },
> -    [VIRT_PLIC] =     {  0xc000000,  0x4000000 },
> -    [VIRT_UART0] =    { 0x10000000,      0x100 },
> -    [VIRT_VIRTIO] =   { 0x10001000,     0x1000 },
> -    [VIRT_DRAM] =     { 0x80000000,        0x0 },
> +    [VIRT_DEBUG] =       {        0x0,         0x100 },
> +    [VIRT_MROM] =        {     0x1000,       0x11000 },
> +    [VIRT_TEST] =        {   0x100000,        0x1000 },
> +    [VIRT_CLINT] =       {  0x2000000,       0x10000 },
> +    [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
> +    [VIRT_UART0] =       { 0x10000000,         0x100 },
> +    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
> +    [VIRT_DRAM] =        { 0x80000000,           0x0 },
>  };
>  
>  static uint64_t load_kernel(const char *kernel_filename)
> 

[Qemu-devel] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe

[Alistair Francis]

Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
---
 default-configs/riscv32-softmmu.mak |   6 +-
 default-configs/riscv64-softmmu.mak |   6 +-
 hw/riscv/virt.c                     | 131 +++++++++++++++++++++++++++-
 include/hw/riscv/virt.h             |  13 ++-
 4 files changed, 152 insertions(+), 4 deletions(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 7937c69e22..3e3d195f37 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -1,7 +1,11 @@
 # Default configuration for riscv-softmmu
 
+include pci.mak
+
 CONFIG_SERIAL=y
 CONFIG_VIRTIO_MMIO=y
-include virtio.mak
 
 CONFIG_CADENCE=y
+
+CONFIG_PCI_GENERIC=y
+CONFIG_PCI_XILINX=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 7937c69e22..3e3d195f37 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -1,7 +1,11 @@
 # Default configuration for riscv-softmmu
 
+include pci.mak
+
 CONFIG_SERIAL=y
 CONFIG_VIRTIO_MMIO=y
-include virtio.mak
 
 CONFIG_CADENCE=y
+
+CONFIG_PCI_GENERIC=y
+CONFIG_PCI_XILINX=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6b6fa39aaa..e7f0716fb6 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -39,6 +39,8 @@
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "exec/address-spaces.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
 #include "elf.h"
 
 #include <libfdt.h>
@@ -55,6 +57,9 @@ static const struct MemmapEntry {
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
     [VIRT_DRAM] =        { 0x80000000,           0x0 },
+    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
+    [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
+    [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
 };
 
 static uint64_t load_kernel(const char *kernel_filename)
@@ -98,6 +103,51 @@ static hwaddr load_initrd(const char *filename, uint64_t mem_size,
     return *start + size;
 }
 
+static void create_pcie_irq_map(void *fdt, char *nodename,
+                                uint32_t plic_phandle)
+{
+    int pin, dev;
+    uint32_t
+        full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
+    uint32_t *irq_map = full_irq_map;
+
+    /* This code creates a standard swizzle of interrupts such that
+     * each device's first interrupt is based on it's PCI_SLOT number.
+     * (See pci_swizzle_map_irq_fn())
+     *
+     * We only need one entry per interrupt in the table (not one per
+     * possible slot) seeing the interrupt-map-mask will allow the table
+     * to wrap to any number of devices.
+     */
+    for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+        int devfn = dev * 0x8;
+
+        for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+            int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+            int i = 0;
+
+            irq_map[i] = cpu_to_be32(devfn << 8);
+
+            i += FDT_PCI_ADDR_CELLS;
+            irq_map[i] = cpu_to_be32(pin + 1);
+
+            i += FDT_PCI_INT_CELLS;
+            irq_map[i++] = cpu_to_be32(plic_phandle);
+
+            i += FDT_PLIC_ADDR_CELLS;
+            irq_map[i] = cpu_to_be32(irq_nr);
+
+            irq_map += FDT_INT_MAP_WIDTH;
+        }
+    }
+
+    qemu_fdt_setprop(fdt, nodename, "interrupt-map",
+                     full_irq_map, sizeof(full_irq_map));
+
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+                           0x1800, 0, 0, 0x7);
+}
+
 static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     uint64_t mem_size, const char *cmdline)
 {
@@ -203,7 +253,10 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
         (long)memmap[VIRT_PLIC].base);
     qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
+                           FDT_PLIC_ADDR_CELLS);
+    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
+                          FDT_PLIC_INT_CELLS);
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
@@ -233,6 +286,33 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
         g_free(nodename);
     }
 
+    nodename = g_strdup_printf("/soc/pci@%lx",
+        (long) memmap[VIRT_PCIE_ECAM].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
+                           FDT_PCI_ADDR_CELLS);
+    qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
+                           FDT_PCI_INT_CELLS);
+    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible",
+                            "pci-host-ecam-generic");
+    qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+    qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
+    qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
+                           memmap[VIRT_PCIE_ECAM].base /
+                               PCIE_MMCFG_SIZE_MIN - 1);
+    qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
+                           0, memmap[VIRT_PCIE_ECAM].size);
+    qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
+        1, FDT_PCI_RANGE_IOPORT, 2, 0,
+        2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
+        1, FDT_PCI_RANGE_MMIO,
+        2, memmap[VIRT_PCIE_MMIO].base,
+        2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
+    create_pcie_irq_map(fdt, nodename, plic_phandle);
+    g_free(nodename);
+
     nodename = g_strdup_printf("/test@%lx",
         (long)memmap[VIRT_TEST].base);
     qemu_fdt_add_subnode(fdt, nodename);
@@ -263,6 +343,47 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     return fdt;
 }
 
+
+static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
+                                          hwaddr ecam_base, hwaddr ecam_size,
+                                          hwaddr mmio_base, hwaddr mmio_size,
+                                          hwaddr pio_base,
+                                          DeviceState *plic, bool link_up)
+{
+    DeviceState *dev;
+    MemoryRegion *ecam_alias, *ecam_reg;
+    MemoryRegion *mmio_alias, *mmio_reg;
+    qemu_irq irq;
+    int i;
+
+    dev = qdev_create(NULL, TYPE_GPEX_HOST);
+
+    qdev_init_nofail(dev);
+
+    ecam_alias = g_new0(MemoryRegion, 1);
+    ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
+                             ecam_reg, 0, ecam_size);
+    memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
+
+    mmio_alias = g_new0(MemoryRegion, 1);
+    mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+    memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
+                             mmio_reg, mmio_base, mmio_size);
+    memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
+
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
+
+    for (i = 0; i < GPEX_NUM_IRQS; i++) {
+        irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
+        gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
+    }
+
+    return dev;
+}
+
 static void riscv_virt_board_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = virt_memmap;
@@ -385,6 +506,14 @@ static void riscv_virt_board_init(MachineState *machine)
             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
     }
 
+    gpex_pcie_init(system_memory,
+                         memmap[VIRT_PCIE_ECAM].base,
+                         memmap[VIRT_PCIE_ECAM].size,
+                         memmap[VIRT_PCIE_MMIO].base,
+                         memmap[VIRT_PCIE_MMIO].size,
+                         memmap[VIRT_PCIE_PIO].base,
+                         DEVICE(s->plic), true);
+
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
         serial_hd(0), DEVICE_LITTLE_ENDIAN);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7cb2742070..2cce019aca 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -38,13 +38,17 @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
-    VIRT_DRAM
+    VIRT_DRAM,
+    VIRT_PCIE_MMIO,
+    VIRT_PCIE_PIO,
+    VIRT_PCIE_ECAM
 };
 
 enum {
     UART0_IRQ = 10,
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
+    PCIE_IRQ = 0x20, /* 32 to 35 */
     VIRTIO_NDEV = 0x35
 };
 
@@ -62,6 +66,13 @@ enum {
 #define VIRT_PLIC_CONTEXT_BASE 0x200000
 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
 
+#define FDT_PCI_ADDR_CELLS    3
+#define FDT_PCI_INT_CELLS     1
+#define FDT_PLIC_ADDR_CELLS   0
+#define FDT_PLIC_INT_CELLS    1
+#define FDT_INT_MAP_WIDTH     (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
+                               FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
+
 #if defined(TARGET_RISCV32)
 #define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
 #elif defined(TARGET_RISCV64)
-- 
2.19.1

Re: [Qemu-devel] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe

[Logan Gunthorpe]

On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>

Reviewed-by: Logan Gunthorpe <logang@deltatee.com>


> diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
> index 7937c69e22..3e3d195f37 100644
> --- a/default-configs/riscv32-softmmu.mak
> +++ b/default-configs/riscv32-softmmu.mak
> @@ -1,7 +1,11 @@
>  # Default configuration for riscv-softmmu
>  
> +include pci.mak
> +
>  CONFIG_SERIAL=y
>  CONFIG_VIRTIO_MMIO=y
> -include virtio.mak
>  
>  CONFIG_CADENCE=y
> +
> +CONFIG_PCI_GENERIC=y
> +CONFIG_PCI_XILINX=y

Nit: should PCI_XILINX not be in patch 5? It's not used in this patch
and was a bit confusing when reviewing.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:01 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
>
> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
>
>
> > diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
> > index 7937c69e22..3e3d195f37 100644
> > --- a/default-configs/riscv32-softmmu.mak
> > +++ b/default-configs/riscv32-softmmu.mak
> > @@ -1,7 +1,11 @@
> >  # Default configuration for riscv-softmmu
> >
> > +include pci.mak
> > +
> >  CONFIG_SERIAL=y
> >  CONFIG_VIRTIO_MMIO=y
> > -include virtio.mak
> >
> >  CONFIG_CADENCE=y
> > +
> > +CONFIG_PCI_GENERIC=y
> > +CONFIG_PCI_XILINX=y
>
> Nit: should PCI_XILINX not be in patch 5? It's not used in this patch
> and was a bit confusing when reviewing.

It probably should be, I have moved it.

Alistair

>
> Logan

[Qemu-devel] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA

[Alistair Francis]

Enable compile support for VGA devices. This allows the user to conenct
a display by adding '-device bochs-display -display sdl' to their
command line argument.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv32-softmmu.mak | 3 +++
 default-configs/riscv64-softmmu.mak | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 3e3d195f37..05fae82f1b 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -9,3 +9,6 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI_GENERIC=y
 CONFIG_PCI_XILINX=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 3e3d195f37..05fae82f1b 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -9,3 +9,6 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI_GENERIC=y
 CONFIG_PCI_XILINX=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
-- 
2.19.1

Re: [Qemu-devel] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA

[Logan Gunthorpe]

On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Enable compile support for VGA devices. This allows the user to conenct
> a display by adding '-device bochs-display -display sdl' to their
> command line argument.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Logan Gunthorpe <logang@deltatee.com>

> ---
>  default-configs/riscv32-softmmu.mak | 3 +++
>  default-configs/riscv64-softmmu.mak | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
> index 3e3d195f37..05fae82f1b 100644
> --- a/default-configs/riscv32-softmmu.mak
> +++ b/default-configs/riscv32-softmmu.mak
> @@ -9,3 +9,6 @@ CONFIG_CADENCE=y
>  
>  CONFIG_PCI_GENERIC=y
>  CONFIG_PCI_XILINX=y
> +
> +CONFIG_VGA=y
> +CONFIG_VGA_PCI=y
> diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
> index 3e3d195f37..05fae82f1b 100644
> --- a/default-configs/riscv64-softmmu.mak
> +++ b/default-configs/riscv64-softmmu.mak
> @@ -9,3 +9,6 @@ CONFIG_CADENCE=y
>  
>  CONFIG_PCI_GENERIC=y
>  CONFIG_PCI_XILINX=y
> +
> +CONFIG_VGA=y
> +CONFIG_VGA_PCI=y
> 

[Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

Connect the Xilinx PCIe device based on the information in the device
tree stored in the ROM of the HiFish Unleashed board.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c         | 64 +++++++++++++++++++++++++++++++++++++
 include/hw/riscv/sifive_u.h |  4 ++-
 2 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ef07df2442..0c51c61082 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -45,6 +45,8 @@
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "exec/address-spaces.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/xilinx-pcie.h"
 #include "elf.h"
 
 #include <libfdt.h>
@@ -61,6 +63,7 @@ static const struct MemmapEntry {
     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
     [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },
+    [SIFIVE_U_PCIE] =     { 0x2000000000, 0x4000000 },
 };
 
 #define GEM_REVISION        0x10070109
@@ -218,6 +221,32 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
     g_free(nodename);
 
+    nodename = g_strdup_printf("/pci@%lx",
+        (long) memmap[SIFIVE_U_PCIE].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x3);
+    qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible",
+                            "xlnx,axi-pcie-host-1.00.a");
+    qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x20, 0x0, 0x0,
+                           memmap[SIFIVE_U_PCIE].size);
+    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+    qemu_fdt_setprop_cells(fdt, nodename, "ranges", 0x2000000, 0x0,
+                           0x40000000, 0x0, 0x40000000, 0x0, 0x20000000);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_PCIE_IRQ);
+    g_free(nodename);
+
+    nodename = g_strdup_printf("/pci@%lx/interrupt-controller",
+            (long) memmap[SIFIVE_U_PCIE].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x00);
+    qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+    g_free(nodename);
+
     nodename = g_strdup_printf("/soc/uart@%lx",
         (long)memmap[SIFIVE_U_UART0].base);
     qemu_fdt_add_subnode(fdt, nodename);
@@ -236,6 +265,37 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(nodename);
 }
 
+static inline DeviceState *
+xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
+                 hwaddr cfg_base, uint64_t cfg_size,
+                 hwaddr mmio_base, uint64_t mmio_size,
+                 qemu_irq irq, bool link_up)
+{
+    DeviceState *dev;
+    MemoryRegion *cfg, *mmio;
+
+    dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);
+
+    qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
+    qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
+    qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
+    qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
+    qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
+    qdev_prop_set_bit(dev, "link_up", link_up);
+
+    qdev_init_nofail(dev);
+
+    cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
+
+    mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+    memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
+
+    qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
+
+    return dev;
+}
+
 static void riscv_sifive_u_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = sifive_u_memmap;
@@ -375,6 +435,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
                        plic_gpios[SIFIVE_U_GEM_IRQ]);
+
+    xilinx_pcie_init(system_memory, 0, memmap[SIFIVE_U_PCIE].base,
+                     memmap[SIFIVE_U_PCIE].size, 0x40000000, 0x20000000,
+                     qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_PCIE_IRQ), true);
 }
 
 static void riscv_sifive_u_machine_init(MachineClass *mc)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e8b4d9ffa3..e7292ea83b 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -53,12 +53,14 @@ enum {
     SIFIVE_U_UART0,
     SIFIVE_U_UART1,
     SIFIVE_U_DRAM,
-    SIFIVE_U_GEM
+    SIFIVE_U_GEM,
+    SIFIVE_U_PCIE
 };
 
 enum {
     SIFIVE_U_UART0_IRQ = 3,
     SIFIVE_U_UART1_IRQ = 4,
+    SIFIVE_U_PCIE_IRQ = 0x20,
     SIFIVE_U_GEM_IRQ = 0x35
 };
 
-- 
2.19.1

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Connect the Xilinx PCIe device based on the information in the device
> tree stored in the ROM of the HiFish Unleashed board.

I only briefly tested this patch but could not get any PCI devices to
come up with the sifive_u machine. Depending on the kernel I tried, it
either failed to initialize a Xilinx PCIe (likely due to a mismatch with
the DT) or it appears to successfully initialize a Microsemi device but
did not enumerate any devices underneath.

In any case, it would be nice if the Microsemi/Xilinx confusion was at
least explained in the commit message.

Thanks,

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Connect the Xilinx PCIe device based on the information in the device
> > tree stored in the ROM of the HiFish Unleashed board.
>
> I only briefly tested this patch but could not get any PCI devices to
> come up with the sifive_u machine. Depending on the kernel I tried, it
> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> the DT) or it appears to successfully initialize a Microsemi device but
> did not enumerate any devices underneath.

That seems like either a kernel or bbl issue.

You need to make sure that bbl doesn't edit the device tree (to add
the Microsemi device or remove the Xilinx one) and ensure your kernel
supports the Xilinx one.

>
> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> least explained in the commit message.

What should we say? The QEMU machine accurately models the real
hardware which reports a Xilinx PCIe. The confusion generally appears
above QEMU where people are used to using the MicroSemi one.

Alistair

>
> Thanks,
>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 11:32 a.m., Alistair Francis wrote:
> That seems like either a kernel or bbl issue.
> 
> You need to make sure that bbl doesn't edit the device tree (to add
> the Microsemi device or remove the Xilinx one) and ensure your kernel
> supports the Xilinx one.

Ok, how do I stop bbl from editing the device tree? I have a kernel with
Xilinx PCI support but it fails initializing on that machine (see below).

>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>> least explained in the commit message.
> 
> What should we say? The QEMU machine accurately models the real
> hardware which reports a Xilinx PCIe. The confusion generally appears
> above QEMU where people are used to using the MicroSemi one.

Maybe describing the bbl issue and what to do to overcome it would be
sufficient.

Logan





[    0.312000] xilinx-pcie 2000000000.pci: PCIe Link is UP
[    0.316000] xilinx-pcie 2000000000.pci: host bridge /pci@2000000000
ranges:
[    0.316000] xilinx-pcie 2000000000.pci:   No bus range found for
/pci@2000000000, using [bus 00-ff]
[    0.320000] xilinx-pcie 2000000000.pci:   MEM 0x40000000..0x5fffffff
-> 0x40000000
[    0.320000] xilinx-pcie 2000000000.pci: PCI host bridge to bus 0000:00
[    0.324000] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.324000] pci_bus 0000:00: root bus resource [mem
0x40000000-0x5fffffff]
[    0.332000] pci 0000:00:00.0: bridge configuration invalid ([bus
00-00]), reconfiguring
[    0.336000] pci_bus 0000:01: extended config space not accessible
[    0.340000] pci 0000:00:00.0: PCI bridge to [bus 01]

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:50 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 11:32 a.m., Alistair Francis wrote:
> > That seems like either a kernel or bbl issue.
> >
> > You need to make sure that bbl doesn't edit the device tree (to add
> > the Microsemi device or remove the Xilinx one) and ensure your kernel
> > supports the Xilinx one.
>
> Ok, how do I stop bbl from editing the device tree? I have a kernel with
> Xilinx PCI support but it fails initializing on that machine (see below).

You should just be able to edit the source, grep for "microsemi".

Do you see the MicroSemi PCIe probe in your dmesg?

>
> >> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> >> least explained in the commit message.
> >
> > What should we say? The QEMU machine accurately models the real
> > hardware which reports a Xilinx PCIe. The confusion generally appears
> > above QEMU where people are used to using the MicroSemi one.
>
> Maybe describing the bbl issue and what to do to overcome it would be
> sufficient.

This is not really a QEMU problem though. If you tried to use the
Xilinx PCIe board on hardware you would see the same thing. Most
people don't have a MicroSemi board so most aren't using bbl versions
that are editing it into their device tree.

Alistair

>
> Logan
>
>
>
>
>
> [    0.312000] xilinx-pcie 2000000000.pci: PCIe Link is UP
> [    0.316000] xilinx-pcie 2000000000.pci: host bridge /pci@2000000000
> ranges:
> [    0.316000] xilinx-pcie 2000000000.pci:   No bus range found for
> /pci@2000000000, using [bus 00-ff]
> [    0.320000] xilinx-pcie 2000000000.pci:   MEM 0x40000000..0x5fffffff
> -> 0x40000000
> [    0.320000] xilinx-pcie 2000000000.pci: PCI host bridge to bus 0000:00
> [    0.324000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    0.324000] pci_bus 0000:00: root bus resource [mem
> 0x40000000-0x5fffffff]
> [    0.332000] pci 0000:00:00.0: bridge configuration invalid ([bus
> 00-00]), reconfiguring
> [    0.336000] pci_bus 0000:01: extended config space not accessible
> [    0.340000] pci 0000:00:00.0: PCI bridge to [bus 01]

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 12:02 p.m., Alistair Francis wrote:
>> Ok, how do I stop bbl from editing the device tree? I have a kernel with
>> Xilinx PCI support but it fails initializing on that machine (see below).
> 
> You should just be able to edit the source, grep for "microsemi".

Gross.

> Do you see the MicroSemi PCIe probe in your dmesg?

I do when I have a kernel with microsemi PCI Support (specifically the
one included in the bbl you sent us a while back).

>>
>>>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>>>> least explained in the commit message.
>>>
>>> What should we say? The QEMU machine accurately models the real
>>> hardware which reports a Xilinx PCIe. The confusion generally appears
>>> above QEMU where people are used to using the MicroSemi one.
>>
>> Maybe describing the bbl issue and what to do to overcome it would be
>> sufficient.
> 
> This is not really a QEMU problem though. If you tried to use the
> Xilinx PCIe board on hardware you would see the same thing. Most
> people don't have a MicroSemi board so most aren't using bbl versions
> that are editing it into their device tree.

It's a qemu problem in that people will want to be able to actually use
qemu... somehow. It has to be documented what's required here. You can't
just say that the sifive_u machine won't work and it's someone else's
problem. People using qemu will not be able to figure out there are bbl
issues.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:09 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 12:02 p.m., Alistair Francis wrote:
> >> Ok, how do I stop bbl from editing the device tree? I have a kernel with
> >> Xilinx PCI support but it fails initializing on that machine (see below).
> >
> > You should just be able to edit the source, grep for "microsemi".
>
> Gross.
>
> > Do you see the MicroSemi PCIe probe in your dmesg?
>
> I do when I have a kernel with microsemi PCI Support (specifically the
> one included in the bbl you sent us a while back).

Yeah, so you need to make sure that doesn't happen.

They are practically the same device so they end up conflicting.

>
> >>
> >>>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> >>>> least explained in the commit message.
> >>>
> >>> What should we say? The QEMU machine accurately models the real
> >>> hardware which reports a Xilinx PCIe. The confusion generally appears
> >>> above QEMU where people are used to using the MicroSemi one.
> >>
> >> Maybe describing the bbl issue and what to do to overcome it would be
> >> sufficient.
> >
> > This is not really a QEMU problem though. If you tried to use the
> > Xilinx PCIe board on hardware you would see the same thing. Most
> > people don't have a MicroSemi board so most aren't using bbl versions
> > that are editing it into their device tree.
>
> It's a qemu problem in that people will want to be able to actually use
> qemu... somehow. It has to be documented what's required here. You can't
> just say that the sifive_u machine won't work and it's someone else's
> problem. People using qemu will not be able to figure out there are bbl
> issues.

I'm not saying the SiFive U won't work.

For people who have modified the standard bbl to edit the device tree
before passing it to Linux to add the MicroSemi PCIe node, it won't
work. That's a very small number of people who have modified the
standard boot loader. I don't think we need to document how those
people get back to the default set-up.

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 12:16 p.m., Alistair Francis wrote:
>>> Do you see the MicroSemi PCIe probe in your dmesg?
>>
>> I do when I have a kernel with microsemi PCI Support (specifically the
>> one included in the bbl you sent us a while back).
> 
> Yeah, so you need to make sure that doesn't happen.

Well, I also have a kernel (one I've built myself) without microsemi
support, but with Xilinx support and it also doesn't work (see my dmesg
logs I sent).

> For people who have modified the standard bbl to edit the device tree
> before passing it to Linux to add the MicroSemi PCIe node, it won't
> work. That's a very small number of people who have modified the
> standard boot loader. I don't think we need to document how those
> people get back to the default set-up.

I have not done that. And it's not working for me.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 12:16 p.m., Alistair Francis wrote:
> >>> Do you see the MicroSemi PCIe probe in your dmesg?
> >>
> >> I do when I have a kernel with microsemi PCI Support (specifically the
> >> one included in the bbl you sent us a while back).
> >
> > Yeah, so you need to make sure that doesn't happen.
>
> Well, I also have a kernel (one I've built myself) without microsemi
> support, but with Xilinx support and it also doesn't work (see my dmesg
> logs I sent).

So this one should work.

>
> > For people who have modified the standard bbl to edit the device tree
> > before passing it to Linux to add the MicroSemi PCIe node, it won't
> > work. That's a very small number of people who have modified the
> > standard boot loader. I don't think we need to document how those
> > people get back to the default set-up.
>
> I have not done that. And it's not working for me.

If you haven't done this then how can Linux know to probe the
MicroSemi PCIe root complex?

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 12:21 p.m., Alistair Francis wrote:
> On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>> Well, I also have a kernel (one I've built myself) without microsemi
>> support, but with Xilinx support and it also doesn't work (see my dmesg
>> logs I sent).
> 
> So this one should work.

It does not, see the dmesgs I sent a few emails ago.

>>
>>> For people who have modified the standard bbl to edit the device tree
>>> before passing it to Linux to add the MicroSemi PCIe node, it won't
>>> work. That's a very small number of people who have modified the
>>> standard boot loader. I don't think we need to document how those
>>> people get back to the default set-up.
>>
>> I have not done that. And it's not working for me.
> 
> If you haven't done this then how can Linux know to probe the
> MicroSemi PCIe root complex?

Oh, well actually, in this case I was using the bbl/kernel you sent us,
so I'm not actually sure what's in it. The stuff I built myself doesn't
have any of the microsemi stuff, so it sounds like all that was a red
herring.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:25 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 12:21 p.m., Alistair Francis wrote:
> > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >> Well, I also have a kernel (one I've built myself) without microsemi
> >> support, but with Xilinx support and it also doesn't work (see my dmesg
> >> logs I sent).
> >
> > So this one should work.
>
> It does not, see the dmesgs I sent a few emails ago.
>
> >>
> >>> For people who have modified the standard bbl to edit the device tree
> >>> before passing it to Linux to add the MicroSemi PCIe node, it won't
> >>> work. That's a very small number of people who have modified the
> >>> standard boot loader. I don't think we need to document how those
> >>> people get back to the default set-up.
> >>
> >> I have not done that. And it's not working for me.
> >
> > If you haven't done this then how can Linux know to probe the
> > MicroSemi PCIe root complex?
>
> Oh, well actually, in this case I was using the bbl/kernel you sent us,
> so I'm not actually sure what's in it. The stuff I built myself doesn't
> have any of the microsemi stuff, so it sounds like all that was a red
> herring.

Ah ok. There was some confusion there then.

So now it sounds like it's not working and there is no MicroSemi
device. I will check and see what I find.

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:51 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Nov 21, 2018 at 11:25 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >
> >
> >
> > On 2018-11-21 12:21 p.m., Alistair Francis wrote:
> > > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> > >> Well, I also have a kernel (one I've built myself) without microsemi
> > >> support, but with Xilinx support and it also doesn't work (see my dmesg
> > >> logs I sent).
> > >
> > > So this one should work.
> >
> > It does not, see the dmesgs I sent a few emails ago.
> >
> > >>
> > >>> For people who have modified the standard bbl to edit the device tree
> > >>> before passing it to Linux to add the MicroSemi PCIe node, it won't
> > >>> work. That's a very small number of people who have modified the
> > >>> standard boot loader. I don't think we need to document how those
> > >>> people get back to the default set-up.
> > >>
> > >> I have not done that. And it's not working for me.
> > >
> > > If you haven't done this then how can Linux know to probe the
> > > MicroSemi PCIe root complex?
> >
> > Oh, well actually, in this case I was using the bbl/kernel you sent us,
> > so I'm not actually sure what's in it. The stuff I built myself doesn't
> > have any of the microsemi stuff, so it sounds like all that was a red
> > herring.
>
> Ah ok. There was some confusion there then.
>
> So now it sounds like it's not working and there is no MicroSemi
> device. I will check and see what I find.

Yep, I have no idea.

The last time I tested this it worked (although I might not have
tested interrupts) and now it doesn't. Nothing has changed in the
series, my guest software has changed though. I can see the root
complex, but no devices underneath it.

Sorry for the confusion with the MicroSemi PCIe root complex.

I think I'll just drop this patch. It doesn't work for 32-bit guests,
but I would like to model the hardware so I don't want to change the
addresses. We can revisit this in the future along with the gpex high
MMIO support and USB support.

Alistair

>
> Alistair
>
> >
> > Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 2:54 p.m., Alistair Francis wrote:
> The last time I tested this it worked (although I might not have
> tested interrupts) and now it doesn't. Nothing has changed in the
> series, my guest software has changed though. I can see the root
> complex, but no devices underneath it.
> 
> Sorry for the confusion with the MicroSemi PCIe root complex.
> 
> I think I'll just drop this patch. It doesn't work for 32-bit guests,
> but I would like to model the hardware so I don't want to change the
> addresses. We can revisit this in the future along with the gpex high
> MMIO support and USB support.

Yeah, I'm less concerned about all the board variant stuff as I am about
having something actually work. I don't want to have to jump through any
bbl hoops or anything to use it if it doesn't work out of the box. And
you're right, getting the virt pci support upstream seems more important
and this issue can be revisited later.

On an slight tangent: what root device do you use with the sifive_u
machine? I can't find any virtual hardware that works. If I had PCI I
could use NVMe, but that's not working. And for this reason I've only
been using the 'virt' device.

Thanks,

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 2:01 PM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 2:54 p.m., Alistair Francis wrote:
> > The last time I tested this it worked (although I might not have
> > tested interrupts) and now it doesn't. Nothing has changed in the
> > series, my guest software has changed though. I can see the root
> > complex, but no devices underneath it.
> >
> > Sorry for the confusion with the MicroSemi PCIe root complex.
> >
> > I think I'll just drop this patch. It doesn't work for 32-bit guests,
> > but I would like to model the hardware so I don't want to change the
> > addresses. We can revisit this in the future along with the gpex high
> > MMIO support and USB support.
>
> Yeah, I'm less concerned about all the board variant stuff as I am about
> having something actually work. I don't want to have to jump through any
> bbl hoops or anything to use it if it doesn't work out of the box. And
> you're right, getting the virt pci support upstream seems more important
> and this issue can be revisited later.
>
> On an slight tangent: what root device do you use with the sifive_u
> machine? I can't find any virtual hardware that works. If I had PCI I
> could use NVMe, but that's not working. And for this reason I've only
> been using the 'virt' device.

Yeah, it's a real pain. I had a go at adding the SD card [1] but never
got it fully working. Normally I just hack in the virtIO MMIO regions
and use those.

1: https://github.com/alistair23/qemu/tree/mainline/alistair/sifive_spi.next
    I just did a quick rebase, fully untested

Alistair

>
> Thanks,
>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 3:09 p.m., Alistair Francis wrote:
> Yeah, it's a real pain. I had a go at adding the SD card [1] but never
> got it fully working. Normally I just hack in the virtIO MMIO regions
> and use those.
> 
> 1: https://github.com/alistair23/qemu/tree/mainline/alistair/sifive_spi.next
>     I just did a quick rebase, fully untested

Ah, so very much work in progress. I'll stick with the virt machine for
the time being.

Thanks,

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 14:01:34 PST (-0800), logang@deltatee.com wrote:
>
>
> On 2018-11-21 2:54 p.m., Alistair Francis wrote:
>> The last time I tested this it worked (although I might not have
>> tested interrupts) and now it doesn't. Nothing has changed in the
>> series, my guest software has changed though. I can see the root
>> complex, but no devices underneath it.
>>
>> Sorry for the confusion with the MicroSemi PCIe root complex.
>>
>> I think I'll just drop this patch. It doesn't work for 32-bit guests,
>> but I would like to model the hardware so I don't want to change the
>> addresses. We can revisit this in the future along with the gpex high
>> MMIO support and USB support.
>
> Yeah, I'm less concerned about all the board variant stuff as I am about
> having something actually work. I don't want to have to jump through any
> bbl hoops or anything to use it if it doesn't work out of the box. And
> you're right, getting the virt pci support upstream seems more important
> and this issue can be revisited later.
>
> On an slight tangent: what root device do you use with the sifive_u
> machine? I can't find any virtual hardware that works. If I had PCI I
> could use NVMe, but that's not working. And for this reason I've only
> been using the 'virt' device.

I've only been using the virt device as well.

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>>
>>
>>
>> On 2018-11-21 12:16 p.m., Alistair Francis wrote:
>> >>> Do you see the MicroSemi PCIe probe in your dmesg?
>> >>
>> >> I do when I have a kernel with microsemi PCI Support (specifically the
>> >> one included in the bbl you sent us a while back).
>> >
>> > Yeah, so you need to make sure that doesn't happen.
>>
>> Well, I also have a kernel (one I've built myself) without microsemi
>> support, but with Xilinx support and it also doesn't work (see my dmesg
>> logs I sent).
>
> So this one should work.
>
>>
>> > For people who have modified the standard bbl to edit the device tree
>> > before passing it to Linux to add the MicroSemi PCIe node, it won't
>> > work. That's a very small number of people who have modified the
>> > standard boot loader. I don't think we need to document how those
>> > people get back to the default set-up.
>>
>> I have not done that. And it's not working for me.
>
> If you haven't done this then how can Linux know to probe the
> MicroSemi PCIe root complex?

BBL passes this through from the FSBL, which has the DTB compiled in:

https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/ux00_fsbl.dts#L405

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 1:37 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistair23@gmail.com wrote:
> > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >>
> >>
> >>
> >> On 2018-11-21 12:16 p.m., Alistair Francis wrote:
> >> >>> Do you see the MicroSemi PCIe probe in your dmesg?
> >> >>
> >> >> I do when I have a kernel with microsemi PCI Support (specifically the
> >> >> one included in the bbl you sent us a while back).
> >> >
> >> > Yeah, so you need to make sure that doesn't happen.
> >>
> >> Well, I also have a kernel (one I've built myself) without microsemi
> >> support, but with Xilinx support and it also doesn't work (see my dmesg
> >> logs I sent).
> >
> > So this one should work.
> >
> >>
> >> > For people who have modified the standard bbl to edit the device tree
> >> > before passing it to Linux to add the MicroSemi PCIe node, it won't
> >> > work. That's a very small number of people who have modified the
> >> > standard boot loader. I don't think we need to document how those
> >> > people get back to the default set-up.
> >>
> >> I have not done that. And it's not working for me.
> >
> > If you haven't done this then how can Linux know to probe the
> > MicroSemi PCIe root complex?
>
> BBL passes this through from the FSBL, which has the DTB compiled in:
>
> https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/ux00_fsbl.dts#L405

That's fairly new though. Our boards show a Xilinx PCIe device.

Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 14:01:10 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Nov 21, 2018 at 1:37 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistair23@gmail.com wrote:
>> > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>> >>
>> >>
>> >>
>> >> On 2018-11-21 12:16 p.m., Alistair Francis wrote:
>> >> >>> Do you see the MicroSemi PCIe probe in your dmesg?
>> >> >>
>> >> >> I do when I have a kernel with microsemi PCI Support (specifically the
>> >> >> one included in the bbl you sent us a while back).
>> >> >
>> >> > Yeah, so you need to make sure that doesn't happen.
>> >>
>> >> Well, I also have a kernel (one I've built myself) without microsemi
>> >> support, but with Xilinx support and it also doesn't work (see my dmesg
>> >> logs I sent).
>> >
>> > So this one should work.
>> >
>> >>
>> >> > For people who have modified the standard bbl to edit the device tree
>> >> > before passing it to Linux to add the MicroSemi PCIe node, it won't
>> >> > work. That's a very small number of people who have modified the
>> >> > standard boot loader. I don't think we need to document how those
>> >> > people get back to the default set-up.
>> >>
>> >> I have not done that. And it's not working for me.
>> >
>> > If you haven't done this then how can Linux know to probe the
>> > MicroSemi PCIe root complex?
>>
>> BBL passes this through from the FSBL, which has the DTB compiled in:
>>
>> https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/ux00_fsbl.dts#L405
>
> That's fairly new though. Our boards show a Xilinx PCIe device.

Presumably you have the Xilinx motherboards, then?  That would mean you have a 
FSBL that was compiled with the device tree to match, which is the right thing 
to do.  Right now there's no way of probing for the motherboard, though at some 
point we designed a scheme to do so it's just not implemented yet.

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 12:02 p.m., Alistair Francis wrote:
> On Wed, Nov 21, 2018 at 10:50 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>>
>>
>>
>> On 2018-11-21 11:32 a.m., Alistair Francis wrote:
>>> That seems like either a kernel or bbl issue.
>>>
>>> You need to make sure that bbl doesn't edit the device tree (to add
>>> the Microsemi device or remove the Xilinx one) and ensure your kernel
>>> supports the Xilinx one.
>>
>> Ok, how do I stop bbl from editing the device tree? I have a kernel with
>> Xilinx PCI support but it fails initializing on that machine (see below).
> 
> You should just be able to edit the source, grep for "microsemi".

I don't see any "microsemi" in my riscv-pk source...

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:15 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 12:02 p.m., Alistair Francis wrote:
> > On Wed, Nov 21, 2018 at 10:50 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >>
> >>
> >>
> >> On 2018-11-21 11:32 a.m., Alistair Francis wrote:
> >>> That seems like either a kernel or bbl issue.
> >>>
> >>> You need to make sure that bbl doesn't edit the device tree (to add
> >>> the Microsemi device or remove the Xilinx one) and ensure your kernel
> >>> supports the Xilinx one.
> >>
> >> Ok, how do I stop bbl from editing the device tree? I have a kernel with
> >> Xilinx PCI support but it fails initializing on that machine (see below).
> >
> > You should just be able to edit the source, grep for "microsemi".
>
> I don't see any "microsemi" in my riscv-pk source...

msemi maybe?

The compatible sting is: ms-pf,axi-pcie-host

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 12:18 p.m., Alistair Francis wrote:
>>>
>>> You should just be able to edit the source, grep for "microsemi".
>>
>> I don't see any "microsemi" in my riscv-pk source...
> 
> msemi maybe?
> 
> The compatible sting is: ms-pf,axi-pcie-host

None of the above.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>>
>>
>>
>> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
>> > Connect the Xilinx PCIe device based on the information in the device
>> > tree stored in the ROM of the HiFish Unleashed board.
>>
>> I only briefly tested this patch but could not get any PCI devices to
>> come up with the sifive_u machine. Depending on the kernel I tried, it
>> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
>> the DT) or it appears to successfully initialize a Microsemi device but
>> did not enumerate any devices underneath.
>
> That seems like either a kernel or bbl issue.
>
> You need to make sure that bbl doesn't edit the device tree (to add
> the Microsemi device or remove the Xilinx one) and ensure your kernel
> supports the Xilinx one.
>
>>
>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>> least explained in the commit message.
>
> What should we say? The QEMU machine accurately models the real
> hardware which reports a Xilinx PCIe. The confusion generally appears
> above QEMU where people are used to using the MicroSemi one.

I think the real issue here is that "sifive_u" doesn't actually fully describe 
the device we're trying to emulate.  Is it a:

* Generic SiFive U core?  In that case we just have a 64-bit core and 
  essentially no devices.  This is kind of useless.
* A HiFive Unleashed?  In that case there's no PCIe, as it requires an 
  expansion board.
* A HiFive Unleashed + VC707?  Here we have Xilinx PCIe.
* A HiFive Unleashed + Microsemi Expansion?  Here have Microsemi PCIe.

There's a tradeoff between accurately emulating the hardware and blowing up the 
amount of targets we support in QEMU.  We went through this discussion before 
and ended up where we are now, but maybe it's best to go have the discussion 
again?

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistair23@gmail.com wrote:
> > On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >>
> >>
> >>
> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> >> > Connect the Xilinx PCIe device based on the information in the device
> >> > tree stored in the ROM of the HiFish Unleashed board.
> >>
> >> I only briefly tested this patch but could not get any PCI devices to
> >> come up with the sifive_u machine. Depending on the kernel I tried, it
> >> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> >> the DT) or it appears to successfully initialize a Microsemi device but
> >> did not enumerate any devices underneath.
> >
> > That seems like either a kernel or bbl issue.
> >
> > You need to make sure that bbl doesn't edit the device tree (to add
> > the Microsemi device or remove the Xilinx one) and ensure your kernel
> > supports the Xilinx one.
> >
> >>
> >> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> >> least explained in the commit message.
> >
> > What should we say? The QEMU machine accurately models the real
> > hardware which reports a Xilinx PCIe. The confusion generally appears
> > above QEMU where people are used to using the MicroSemi one.
>
> I think the real issue here is that "sifive_u" doesn't actually fully describe
> the device we're trying to emulate.  Is it a:
>
> * Generic SiFive U core?  In that case we just have a 64-bit core and
>   essentially no devices.  This is kind of useless.
> * A HiFive Unleashed?  In that case there's no PCIe, as it requires an
>   expansion board.
> * A HiFive Unleashed + VC707?  Here we have Xilinx PCIe.
> * A HiFive Unleashed + Microsemi Expansion?  Here have Microsemi PCIe.

This isn't even always consistent. For example the sifive_u machine
exists for 32-bit cores, but the PCIe address reported by the hardware
only works for 64-bit machines.

So we need a trade off between accurately modelling the hardware or
having 32-bit support.

>
> There's a tradeoff between accurately emulating the hardware and blowing up the
> amount of targets we support in QEMU.  We went through this discussion before
> and ended up where we are now, but maybe it's best to go have the discussion
> again?

Up to you, it is your board :)

I think it makes more sense to remove these generic boards (that is
what the virt board is for) and model real hardware boards.

Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 13:49:53 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistair23@gmail.com wrote:
>> > On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>> >>
>> >>
>> >>
>> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
>> >> > Connect the Xilinx PCIe device based on the information in the device
>> >> > tree stored in the ROM of the HiFish Unleashed board.
>> >>
>> >> I only briefly tested this patch but could not get any PCI devices to
>> >> come up with the sifive_u machine. Depending on the kernel I tried, it
>> >> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
>> >> the DT) or it appears to successfully initialize a Microsemi device but
>> >> did not enumerate any devices underneath.
>> >
>> > That seems like either a kernel or bbl issue.
>> >
>> > You need to make sure that bbl doesn't edit the device tree (to add
>> > the Microsemi device or remove the Xilinx one) and ensure your kernel
>> > supports the Xilinx one.
>> >
>> >>
>> >> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>> >> least explained in the commit message.
>> >
>> > What should we say? The QEMU machine accurately models the real
>> > hardware which reports a Xilinx PCIe. The confusion generally appears
>> > above QEMU where people are used to using the MicroSemi one.
>>
>> I think the real issue here is that "sifive_u" doesn't actually fully describe
>> the device we're trying to emulate.  Is it a:
>>
>> * Generic SiFive U core?  In that case we just have a 64-bit core and
>>   essentially no devices.  This is kind of useless.
>> * A HiFive Unleashed?  In that case there's no PCIe, as it requires an
>>   expansion board.
>> * A HiFive Unleashed + VC707?  Here we have Xilinx PCIe.
>> * A HiFive Unleashed + Microsemi Expansion?  Here have Microsemi PCIe.
>
> This isn't even always consistent. For example the sifive_u machine
> exists for 32-bit cores, but the PCIe address reported by the hardware
> only works for 64-bit machines.
>
> So we need a trade off between accurately modelling the hardware or
> having 32-bit support.

Yep, there's another issue.

>> There's a tradeoff between accurately emulating the hardware and blowing up the
>> amount of targets we support in QEMU.  We went through this discussion before
>> and ended up where we are now, but maybe it's best to go have the discussion
>> again?
>
> Up to you, it is your board :)
>
> I think it makes more sense to remove these generic boards (that is
> what the virt board is for) and model real hardware boards.

That seems reasonable to me.  Is removing boards allowed?  If so I'd be OK 
renaming these to "sifive-hifive1" and "sifive-hifive-unleashed", and possibly 
adding a "sifive-hifive-unleashed-vc707" as it's possible to emulate most of 
that.  Then we at least have accurate names for the boards.

We do have an issue where I'd like to be able to have some system by which we 
can configure the memory map of the target, but maybe that's separate 
discussion.

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 2:15 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 21 Nov 2018 13:49:53 PST (-0800), alistair23@gmail.com wrote:
> > On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> >>
> >> On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistair23@gmail.com wrote:
> >> > On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >> >>
> >> >>
> >> >>
> >> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> >> >> > Connect the Xilinx PCIe device based on the information in the device
> >> >> > tree stored in the ROM of the HiFish Unleashed board.
> >> >>
> >> >> I only briefly tested this patch but could not get any PCI devices to
> >> >> come up with the sifive_u machine. Depending on the kernel I tried, it
> >> >> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> >> >> the DT) or it appears to successfully initialize a Microsemi device but
> >> >> did not enumerate any devices underneath.
> >> >
> >> > That seems like either a kernel or bbl issue.
> >> >
> >> > You need to make sure that bbl doesn't edit the device tree (to add
> >> > the Microsemi device or remove the Xilinx one) and ensure your kernel
> >> > supports the Xilinx one.
> >> >
> >> >>
> >> >> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> >> >> least explained in the commit message.
> >> >
> >> > What should we say? The QEMU machine accurately models the real
> >> > hardware which reports a Xilinx PCIe. The confusion generally appears
> >> > above QEMU where people are used to using the MicroSemi one.
> >>
> >> I think the real issue here is that "sifive_u" doesn't actually fully describe
> >> the device we're trying to emulate.  Is it a:
> >>
> >> * Generic SiFive U core?  In that case we just have a 64-bit core and
> >>   essentially no devices.  This is kind of useless.
> >> * A HiFive Unleashed?  In that case there's no PCIe, as it requires an
> >>   expansion board.
> >> * A HiFive Unleashed + VC707?  Here we have Xilinx PCIe.
> >> * A HiFive Unleashed + Microsemi Expansion?  Here have Microsemi PCIe.
> >
> > This isn't even always consistent. For example the sifive_u machine
> > exists for 32-bit cores, but the PCIe address reported by the hardware
> > only works for 64-bit machines.
> >
> > So we need a trade off between accurately modelling the hardware or
> > having 32-bit support.
>
> Yep, there's another issue.
>
> >> There's a tradeoff between accurately emulating the hardware and blowing up the
> >> amount of targets we support in QEMU.  We went through this discussion before
> >> and ended up where we are now, but maybe it's best to go have the discussion
> >> again?
> >
> > Up to you, it is your board :)
> >
> > I think it makes more sense to remove these generic boards (that is
> > what the virt board is for) and model real hardware boards.
>
> That seems reasonable to me.  Is removing boards allowed?  If so I'd be OK

It's possible, but takes some releases and deprecation warnings.

You can see info about it here:
https://qemu.weilnetz.de/doc/qemu-doc.html#Deprecated-features

As it sounds like no one uses sifive u board (you can't specify a
rootFS) it probably isn't that bad to remove.

> renaming these to "sifive-hifive1" and "sifive-hifive-unleashed", and possibly
> adding a "sifive-hifive-unleashed-vc707" as it's possible to emulate most of
> that.  Then we at least have accurate names for the boards.

That sounds good to me.

>
> We do have an issue where I'd like to be able to have some system by which we
> can configure the memory map of the target, but maybe that's separate
> discussion.

Yeah, that would also be nice, but I think is separate.

Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 14:23:13 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Nov 21, 2018 at 2:15 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Wed, 21 Nov 2018 13:49:53 PST (-0800), alistair23@gmail.com wrote:
>> > On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>> >>
>> >> On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistair23@gmail.com wrote:
>> >> > On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>> >> >>
>> >> >>
>> >> >>
>> >> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
>> >> >> > Connect the Xilinx PCIe device based on the information in the device
>> >> >> > tree stored in the ROM of the HiFish Unleashed board.
>> >> >>
>> >> >> I only briefly tested this patch but could not get any PCI devices to
>> >> >> come up with the sifive_u machine. Depending on the kernel I tried, it
>> >> >> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
>> >> >> the DT) or it appears to successfully initialize a Microsemi device but
>> >> >> did not enumerate any devices underneath.
>> >> >
>> >> > That seems like either a kernel or bbl issue.
>> >> >
>> >> > You need to make sure that bbl doesn't edit the device tree (to add
>> >> > the Microsemi device or remove the Xilinx one) and ensure your kernel
>> >> > supports the Xilinx one.
>> >> >
>> >> >>
>> >> >> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>> >> >> least explained in the commit message.
>> >> >
>> >> > What should we say? The QEMU machine accurately models the real
>> >> > hardware which reports a Xilinx PCIe. The confusion generally appears
>> >> > above QEMU where people are used to using the MicroSemi one.
>> >>
>> >> I think the real issue here is that "sifive_u" doesn't actually fully describe
>> >> the device we're trying to emulate.  Is it a:
>> >>
>> >> * Generic SiFive U core?  In that case we just have a 64-bit core and
>> >>   essentially no devices.  This is kind of useless.
>> >> * A HiFive Unleashed?  In that case there's no PCIe, as it requires an
>> >>   expansion board.
>> >> * A HiFive Unleashed + VC707?  Here we have Xilinx PCIe.
>> >> * A HiFive Unleashed + Microsemi Expansion?  Here have Microsemi PCIe.
>> >
>> > This isn't even always consistent. For example the sifive_u machine
>> > exists for 32-bit cores, but the PCIe address reported by the hardware
>> > only works for 64-bit machines.
>> >
>> > So we need a trade off between accurately modelling the hardware or
>> > having 32-bit support.
>>
>> Yep, there's another issue.
>>
>> >> There's a tradeoff between accurately emulating the hardware and blowing up the
>> >> amount of targets we support in QEMU.  We went through this discussion before
>> >> and ended up where we are now, but maybe it's best to go have the discussion
>> >> again?
>> >
>> > Up to you, it is your board :)
>> >
>> > I think it makes more sense to remove these generic boards (that is
>> > what the virt board is for) and model real hardware boards.
>>
>> That seems reasonable to me.  Is removing boards allowed?  If so I'd be OK
>
> It's possible, but takes some releases and deprecation warnings.
>
> You can see info about it here:
> https://qemu.weilnetz.de/doc/qemu-doc.html#Deprecated-features
>
> As it sounds like no one uses sifive u board (you can't specify a
> rootFS) it probably isn't that bad to remove.

OK, I'll write a patch.

>> renaming these to "sifive-hifive1" and "sifive-hifive-unleashed", and possibly
>> adding a "sifive-hifive-unleashed-vc707" as it's possible to emulate most of
>> that.  Then we at least have accurate names for the boards.
>
> That sounds good to me.
>
>>
>> We do have an issue where I'd like to be able to have some system by which we
>> can configure the memory map of the target, but maybe that's separate
>> discussion.
>
> Yeah, that would also be nice, but I think is separate.
>
> Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Guenter Roeck]

On Wed, Nov 21, 2018 at 02:36:22PM -0800, Palmer Dabbelt wrote:
> On Wed, 21 Nov 2018 14:23:13 PST (-0800), alistair23@gmail.com wrote:
> >On Wed, Nov 21, 2018 at 2:15 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> >>
> >>On Wed, 21 Nov 2018 13:49:53 PST (-0800), alistair23@gmail.com wrote:
> >>> On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> >>>>
> >>>> On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistair23@gmail.com wrote:
> >>>> > On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <logang@deltatee.com> wrote:
> >>>> >>
> >>>> >>
> >>>> >>
> >>>> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> >>>> >> > Connect the Xilinx PCIe device based on the information in the device
> >>>> >> > tree stored in the ROM of the HiFish Unleashed board.
> >>>> >>
> >>>> >> I only briefly tested this patch but could not get any PCI devices to
> >>>> >> come up with the sifive_u machine. Depending on the kernel I tried, it
> >>>> >> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> >>>> >> the DT) or it appears to successfully initialize a Microsemi device but
> >>>> >> did not enumerate any devices underneath.
> >>>> >
> >>>> > That seems like either a kernel or bbl issue.
> >>>> >
> >>>> > You need to make sure that bbl doesn't edit the device tree (to add
> >>>> > the Microsemi device or remove the Xilinx one) and ensure your kernel
> >>>> > supports the Xilinx one.
> >>>> >
> >>>> >>
> >>>> >> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> >>>> >> least explained in the commit message.
> >>>> >
> >>>> > What should we say? The QEMU machine accurately models the real
> >>>> > hardware which reports a Xilinx PCIe. The confusion generally appears
> >>>> > above QEMU where people are used to using the MicroSemi one.
> >>>>
> >>>> I think the real issue here is that "sifive_u" doesn't actually fully describe
> >>>> the device we're trying to emulate.  Is it a:
> >>>>
> >>>> * Generic SiFive U core?  In that case we just have a 64-bit core and
> >>>>   essentially no devices.  This is kind of useless.
> >>>> * A HiFive Unleashed?  In that case there's no PCIe, as it requires an
> >>>>   expansion board.
> >>>> * A HiFive Unleashed + VC707?  Here we have Xilinx PCIe.
> >>>> * A HiFive Unleashed + Microsemi Expansion?  Here have Microsemi PCIe.
> >>>
> >>> This isn't even always consistent. For example the sifive_u machine
> >>> exists for 32-bit cores, but the PCIe address reported by the hardware
> >>> only works for 64-bit machines.
> >>>
> >>> So we need a trade off between accurately modelling the hardware or
> >>> having 32-bit support.
> >>
> >>Yep, there's another issue.
> >>
> >>>> There's a tradeoff between accurately emulating the hardware and blowing up the
> >>>> amount of targets we support in QEMU.  We went through this discussion before
> >>>> and ended up where we are now, but maybe it's best to go have the discussion
> >>>> again?
> >>>
> >>> Up to you, it is your board :)
> >>>
> >>> I think it makes more sense to remove these generic boards (that is
> >>> what the virt board is for) and model real hardware boards.
> >>
> >>That seems reasonable to me.  Is removing boards allowed?  If so I'd be OK
> >
> >It's possible, but takes some releases and deprecation warnings.
> >
> >You can see info about it here:
> >https://qemu.weilnetz.de/doc/qemu-doc.html#Deprecated-features
> >
> >As it sounds like no one uses sifive u board (you can't specify a
> >rootFS) it probably isn't that bad to remove.
> 
FWIW, I absoutely agree. If the board can only be used to boot an initrd,
it is quite pointless to have it around. Actually it is worse than pointless,
since it will result in people wasting their time trying to get it to work.

Guenter

> OK, I'll write a patch.
> 
> >>renaming these to "sifive-hifive1" and "sifive-hifive-unleashed", and possibly
> >>adding a "sifive-hifive-unleashed-vc707" as it's possible to emulate most of
> >>that.  Then we at least have accurate names for the boards.
> >
> >That sounds good to me.
> >
> >>
> >>We do have an issue where I'd like to be able to have some system by which we
> >>can configure the memory map of the target, but maybe that's separate
> >>discussion.
> >
> >Yeah, that would also be nice, but I think is separate.
> >
> >Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
> FWIW, I absoutely agree. If the board can only be used to boot an initrd,
> it is quite pointless to have it around. Actually it is worse than pointless,
> since it will result in people wasting their time trying to get it to work.

As someone who has wasted their time on it, I second this sentiment.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 15:26:01 PST (-0800), logang@deltatee.com wrote:
>
>
> On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
>> FWIW, I absoutely agree. If the board can only be used to boot an initrd,
>> it is quite pointless to have it around. Actually it is worse than pointless,
>> since it will result in people wasting their time trying to get it to work.
>
> As someone who has wasted their time on it, I second this sentiment.

So it sounds like I should target that deprecation patch set for 3.1?  Who 
wants to review it?

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 6:13 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 21 Nov 2018 15:26:01 PST (-0800), logang@deltatee.com wrote:
> >
> >
> > On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
> >> FWIW, I absoutely agree. If the board can only be used to boot an initrd,
> >> it is quite pointless to have it around. Actually it is worse than pointless,
> >> since it will result in people wasting their time trying to get it to work.
> >
> > As someone who has wasted their time on it, I second this sentiment.
>
> So it sounds like I should target that deprecation patch set for 3.1?  Who
> wants to review it?

I think it's a little late for 3.1. Let's leave it for 3.2

Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Palmer Dabbelt]

On Wed, 21 Nov 2018 18:23:26 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Nov 21, 2018 at 6:13 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Wed, 21 Nov 2018 15:26:01 PST (-0800), logang@deltatee.com wrote:
>> >
>> >
>> > On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
>> >> FWIW, I absoutely agree. If the board can only be used to boot an initrd,
>> >> it is quite pointless to have it around. Actually it is worse than pointless,
>> >> since it will result in people wasting their time trying to get it to work.
>> >
>> > As someone who has wasted their time on it, I second this sentiment.
>>
>> So it sounds like I should target that deprecation patch set for 3.1?  Who
>> wants to review it?
>
> I think it's a little late for 3.1. Let's leave it for 3.2

That was my original thought as well, so I'm happy sticking with the plan.

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Guenter Roeck]

Hi Logan,

On Wed, Nov 21, 2018 at 11:05:21AM -0700, Logan Gunthorpe wrote:
> 
> 
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Connect the Xilinx PCIe device based on the information in the device
> > tree stored in the ROM of the HiFish Unleashed board.
> 
> I only briefly tested this patch but could not get any PCI devices to
> come up with the sifive_u machine. Depending on the kernel I tried, it
> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> the DT) or it appears to successfully initialize a Microsemi device but
> did not enumerate any devices underneath.

What kernel configuration, devicetree, and qemu command line do you use
for the sifive_u machine ?

Thanks,
Guenter

> 
> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> least explained in the commit message.
> 
> Thanks,
> 
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

[-- Attachment #1: Type: text/plain, Size: 690 bytes --]



On 2018-11-21 11:36 a.m., Guenter Roeck wrote:
> What kernel configuration, devicetree, and qemu command line do you use
> for the sifive_u machine ?

For kernel configuration, I've tried a couple but I've attached one that
I think makes sense.

The device tree is whatever bbl/qemu are doing (sounds like qemu creates
one and bbl edits it???...).

QEMU Command line is roughly: (though I tweak things constantly and it
doesn't have a working root device at the moment.)

$QEMU -D /tmp/qemu.log -s -nographic -machine sifive_u -m 2G -kernel $BBL \
   -append "console=hvc0 ro root=/dev/vda" \
   -device nvme,drive=nvme0,serial=nvme0 \
   -drive file=nvme0.qcow2,if=none,id=nvme0


Logan

[-- Attachment #2: riscv-config --]
[-- Type: text/plain, Size: 70509 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/riscv 4.20.0-rc3 Kernel Configuration
#

#
# Compiler: riscv64-linux-gnu-gcc (Debian 8.2.0-9) 8.2.0
#
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=80200
CONFIG_CLANG_VERSION=0
CONFIG_IRQ_WORK=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
# CONFIG_AUDIT is not set

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_IRQ_DOMAIN=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_CLOCKEVENTS=y

#
# Timers subsystem
#
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_PSI is not set
CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_BUILD_BIN2C=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
# CONFIG_MEMCG is not set
# CONFIG_BLK_CGROUP is not set
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
# CONFIG_CGROUP_RDMA is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CPUSETS is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_CPUACCT is not set
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
# CONFIG_USERFAULTFD is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
# CONFIG_PERF_EVENTS is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_PROFILING is not set
CONFIG_64BIT=y
CONFIG_RISCV=y
CONFIG_MMU=y
CONFIG_ZONE_DMA32=y
CONFIG_PAGE_OFFSET=0xffffffe000000000
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_PGTABLE_LEVELS=3

#
# Platform type
#
# CONFIG_ARCH_RV32I is not set
CONFIG_ARCH_RV64I=y
# CONFIG_CMODEL_MEDLOW is not set
CONFIG_CMODEL_MEDANY=y
CONFIG_MODULE_SECTIONS=y
# CONFIG_MAXPHYSMEM_2GB is not set
CONFIG_MAXPHYSMEM_128GB=y
CONFIG_SMP=y
CONFIG_NR_CPUS=8
CONFIG_TUNE_GENERIC=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_A=y
CONFIG_FPU=y

#
# Kernel features
#
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250

#
# Boot options
#
# CONFIG_CMDLINE_BOOL is not set

#
# Bus support
#
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_HOST is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCIE_XILINX=y

#
# DesignWare PCI Core Support
#

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set

#
# Power management options
#
# CONFIG_PM is not set

#
# General architecture-dependent options
#
CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_CLK=y
CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_CLONE_BACKWARDS=y
# CONFIG_REFCOUNT_FULL is not set

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_PLUGIN_HOSTCC=""
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_CMDLINE_PARSER is not set
# CONFIG_BLK_WBT is not set
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BLK_SED_OPAL is not set

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
# CONFIG_IOSCHED_BFQ is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y

#
# Memory Management options
#
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
# CONFIG_CMA is not set
# CONFIG_ZPOOL is not set
# CONFIG_ZBUD is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_INTERFACE is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
# CONFIG_XDP_SOCKETS is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
# CONFIG_IP_MULTIPLE_TABLES is not set
# CONFIG_IP_ROUTE_MULTIPATH is not set
# CONFIG_IP_ROUTE_VERBOSE is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
# CONFIG_IP_MROUTE is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_NET_IPVTI is not set
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_INET_RAW_DIAG is not set
# CONFIG_INET_DIAG_DESTROY is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
CONFIG_INET6_XFRM_MODE_TUNNEL=y
CONFIG_INET6_XFRM_MODE_BEET=y
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
# CONFIG_IPV6_VTI is not set
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
CONFIG_HAVE_NET_DSA=y
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=y
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
# CONFIG_NET_SWITCHDEV is not set
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
# CONFIG_BPF_STREAM_PARSER is not set
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set

#
# CFG80211 needs to be enabled for MAC80211
#
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
# CONFIG_NET_DEVLINK is not set
CONFIG_MAY_USE_DEVLINK=y
CONFIG_FAILOVER=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set

#
# Bus devices
#
# CONFIG_CONNECTOR is not set
# CONFIG_GNSS is not set
# CONFIG_MTD is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
# CONFIG_OF_OVERLAY is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=y
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=y
# CONFIG_VIRTIO_BLK_SCSI is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_FC is not set

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_SRAM is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set

#
# Intel MIC & related support
#

#
# Intel MIC Bus Driver
#

#
# SCIF Bus Driver
#

#
# VOP Bus Driver
#

#
# Intel MIC Host Driver
#

#
# Intel MIC Card Driver
#

#
# SCIF Driver
#

#
# Intel MIC Coprocessor State Management (COSM) Drivers
#

#
# VOP Driver
#
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_PCI is not set
# CONFIG_MISC_RTSX_USB is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_MQ_DEFAULT=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_VIRTIO is not set
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_ATA=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_AHCI_CEVA is not set
# CONFIG_AHCI_QORIQ is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
CONFIG_NETDEVICES=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_FC is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_TUN is not set
# CONFIG_TUN_VNET_CROSS_LE is not set
# CONFIG_VETH is not set
CONFIG_VIRTIO_NET=y
# CONFIG_NLMON is not set
# CONFIG_ARCNET is not set

#
# CAIF transport drivers
#

#
# Distributed Switch Architecture drivers
#
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_3COM=y
# CONFIG_VORTEX is not set
# CONFIG_TYPHOON is not set
CONFIG_NET_VENDOR_ADAPTEC=y
# CONFIG_ADAPTEC_STARFIRE is not set
CONFIG_NET_VENDOR_AGERE=y
# CONFIG_ET131X is not set
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALTEON=y
# CONFIG_ACENIC is not set
# CONFIG_ALTERA_TSE is not set
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_PCNET32 is not set
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
# CONFIG_ALX is not set
CONFIG_NET_VENDOR_AURORA=y
# CONFIG_AURORA_NB8800 is not set
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_BCMGENET is not set
# CONFIG_BNX2 is not set
# CONFIG_CNIC is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2X is not set
# CONFIG_SYSTEMPORT is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_BROCADE=y
# CONFIG_BNA is not set
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=y
CONFIG_MACB_USE_HWSTAMP=y
# CONFIG_MACB_PCI is not set
CONFIG_NET_VENDOR_CAVIUM=y
# CONFIG_THUNDER_NIC_PF is not set
# CONFIG_THUNDER_NIC_VF is not set
# CONFIG_THUNDER_NIC_BGX is not set
# CONFIG_THUNDER_NIC_RGX is not set
CONFIG_CAVIUM_PTP=y
# CONFIG_LIQUIDIO is not set
# CONFIG_LIQUIDIO_VF is not set
CONFIG_NET_VENDOR_CHELSIO=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_CHELSIO_T4 is not set
# CONFIG_CHELSIO_T4VF is not set
CONFIG_NET_VENDOR_CISCO=y
# CONFIG_ENIC is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_DEC=y
# CONFIG_NET_TULIP is not set
CONFIG_NET_VENDOR_DLINK=y
# CONFIG_DL2K is not set
# CONFIG_SUNDANCE is not set
CONFIG_NET_VENDOR_EMULEX=y
# CONFIG_BE2NET is not set
CONFIG_NET_VENDOR_EZCHIP=y
# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_HP=y
# CONFIG_HP100 is not set
CONFIG_NET_VENDOR_HUAWEI=y
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
# CONFIG_E1000 is not set
CONFIG_E1000E=y
# CONFIG_IGB is not set
# CONFIG_IGBVF is not set
# CONFIG_IXGB is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
# CONFIG_IGC is not set
# CONFIG_JME is not set
CONFIG_NET_VENDOR_MARVELL=y
# CONFIG_MVMDIO is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
CONFIG_NET_VENDOR_MELLANOX=y
# CONFIG_MLX4_EN is not set
# CONFIG_MLX5_CORE is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8851_MLL is not set
# CONFIG_KSZ884X_PCI is not set
CONFIG_NET_VENDOR_MICROCHIP=y
# CONFIG_LAN743X is not set
CONFIG_NET_VENDOR_MICROSEMI=y
CONFIG_NET_VENDOR_MYRI=y
# CONFIG_MYRI10GE is not set
# CONFIG_FEALNX is not set
CONFIG_NET_VENDOR_NATSEMI=y
# CONFIG_NATSEMI is not set
# CONFIG_NS83820 is not set
CONFIG_NET_VENDOR_NETERION=y
# CONFIG_S2IO is not set
# CONFIG_VXGE is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_8390=y
# CONFIG_NE2K_PCI is not set
CONFIG_NET_VENDOR_NVIDIA=y
# CONFIG_FORCEDETH is not set
CONFIG_NET_VENDOR_OKI=y
# CONFIG_ETHOC is not set
CONFIG_NET_VENDOR_PACKET_ENGINES=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
CONFIG_NET_VENDOR_QLOGIC=y
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
# CONFIG_QLGE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_QED is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
CONFIG_NET_VENDOR_RDC=y
# CONFIG_R6040 is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
CONFIG_R8169=y
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_NET_VENDOR_SAMSUNG=y
# CONFIG_SXGBE_ETH is not set
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
# CONFIG_SFC_FALCON is not set
CONFIG_NET_VENDOR_SILAN=y
# CONFIG_SC92031 is not set
CONFIG_NET_VENDOR_SIS=y
# CONFIG_SIS900 is not set
# CONFIG_SIS190 is not set
CONFIG_NET_VENDOR_SMSC=y
# CONFIG_EPIC100 is not set
# CONFIG_SMSC911X is not set
# CONFIG_SMSC9420 is not set
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
# CONFIG_STMMAC_ETH is not set
CONFIG_NET_VENDOR_SUN=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NIU is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
# CONFIG_TEHUTI is not set
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_ALE is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VIA=y
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_NET_VENDOR_WIZNET=y
# CONFIG_WIZNET_W5100 is not set
# CONFIG_WIZNET_W5300 is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
# CONFIG_MDIO_BCM_UNIMAC is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_THUNDER is not set
CONFIG_PHYLIB=y
CONFIG_SWPHY=y

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_ASIX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_ICPLUS_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROCHIP_T1_PHY is not set
CONFIG_MICROSEMI_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_LAN78XX is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
CONFIG_WLAN=y
# CONFIG_WIRELESS_WDS is not set
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH5K_PCI is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_WLAN_VENDOR_CISCO=y
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_WLAN_VENDOR_INTERSIL=y
# CONFIG_HOSTAP is not set
# CONFIG_PRISM54 is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_WLAN_VENDOR_QUANTENNA=y

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_VMXNET3 is not set
# CONFIG_NETDEVSIM is not set
CONFIG_NET_FAILOVER=y
# CONFIG_ISDN is not set
# CONFIG_NVM is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_RMI4_CORE is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_DEVMEM=y
# CONFIG_DEVKMEM is not set

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_RT288X is not set
# CONFIG_SERIAL_8250_MOXA is not set
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
CONFIG_HVC_DRIVER=y
CONFIG_HVC_RISCV_SBI=y
# CONFIG_VIRTIO_CONSOLE is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=m
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_VIRTIO is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set

#
# PCMCIA character devices
#
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_XILLYBUS is not set

#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
# CONFIG_I2C_CHARDEV is not set
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_RK3X is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_SPI is not set
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
# CONFIG_PPS is not set

#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# CONFIG_PINCTRL is not set
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
# CONFIG_POWER_AVS is not set
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_THERMAL is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AT91_USART is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_REGULATOR is not set
# CONFIG_RC_CORE is not set
# CONFIG_MEDIA_SUPPORT is not set

#
# Graphics support
#
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_DRM=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=y

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
CONFIG_DRM_RADEON=y
# CONFIG_DRM_RADEON_USERPTR is not set
# CONFIG_DRM_AMDGPU is not set

#
# ACP (Audio CoProcessor) Configuration
#

#
# AMD Library routines
#
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_QXL is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_VIRTIO_GPU is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_DUMB_VGA_DAC is not set
# CONFIG_DRM_LVDS_ENCODER is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_TINYDRM is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SM712 is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_PM8941_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# CONFIG_LOGO is not set
# CONFIG_SOUND is not set

#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# I2C HID support
#
# CONFIG_I2C_HID is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_MUSB_HDRC is not set
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_CHAOSKEY is not set

#
# USB Physical Layer drivers
#
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_GADGET is not set
# CONFIG_TYPEC is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_UWB is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_UDMABUF is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO=y
CONFIG_VIRTIO_MENU=y
# CONFIG_VIRTIO_PCI is not set
# CONFIG_VIRTIO_BALLOON is not set
# CONFIG_VIRTIO_INPUT is not set
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_STAGING is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
# CONFIG_CLK_HSDK is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_RISCV_TIMER=y
# CONFIG_MAILBOX is not set
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
# CONFIG_IOMMU_DEBUGFS is not set

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set

#
# Rpmsg drivers
#
# CONFIG_RPMSG_VIRTIO is not set
# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#

#
# Broadcom SoC drivers
#

#
# NXP/Freescale QorIQ SoC drivers
#

#
# i.MX SoC drivers
#

#
# Qualcomm SoC drivers
#
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
# CONFIG_PWM is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_SIFIVE_PLIC=y
# CONFIG_IPACK_BUS is not set
# CONFIG_RESET_CONTROLLER is not set
# CONFIG_FMC is not set

#
# PHY Subsystem
#
# CONFIG_GENERIC_PHY is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_DP is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set
CONFIG_RAS=y

#
# Android
#
# CONFIG_ANDROID is not set
# CONFIG_LIBNVDIMM is not set
# CONFIG_DAX is not set
# CONFIG_NVMEM is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set

#
# File systems
#
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_ENCRYPTION is not set
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_FS_ENCRYPTION is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
# CONFIG_FUSE_FS is not set
# CONFIG_OVERLAY_FS is not set

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_MEMFD_CREATE=y
# CONFIG_CONFIGFS_FS is not set
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=y
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=m
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=m
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_ACOMP2=y
# CONFIG_CRYPTO_RSA is not set
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_ECDH is not set
CONFIG_CRYPTO_MANAGER=m
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=m

#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_AEGIS128L is not set
# CONFIG_CRYPTO_AEGIS256 is not set
# CONFIG_CRYPTO_MORUS640 is not set
# CONFIG_CRYPTO_MORUS1280 is not set
# CONFIG_CRYPTO_SEQIV is not set
CONFIG_CRYPTO_ECHAINIV=m

#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_KEYWRAP is not set

#
# Hash modes
#
# CONFIG_CRYPTO_CMAC is not set
CONFIG_CRYPTO_HMAC=m
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
CONFIG_CRYPTO_SHA256=m
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set

#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DRBG_MENU=m
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
CONFIG_CRYPTO_DRBG=m
CONFIG_CRYPTO_JITTERENTROPY=m
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_STATS is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_ASYMMETRIC_KEY_TYPE is not set

#
# Certificates for signature checking
#
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_PCI_IOMAP=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC64 is not set
# CONFIG_CRC4 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_INTERVAL_TREE=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_DMA_DIRECT_OPS=y
CONFIG_SWIOTLB=y
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
# CONFIG_IRQ_POLL is not set
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_REDUCED=y
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_GDB_SCRIPTS is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_PAGE_OWNER is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_DEBUG_KERNEL=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Lockups and Hangs
#
# CONFIG_SOFTLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_STACKTRACE is not set
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PI_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_PREEMPTIRQ_EVENTS is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_DMA_API_DEBUG is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_SORT is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_BITFIELD is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_MEMTEST is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_SAMPLES is not set
# CONFIG_UBSAN is not set
CONFIG_EARLY_PRINTK=y

[Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Alistair Francis]

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv32-softmmu.mak |  1 +
 default-configs/riscv64-softmmu.mak |  1 +
 hw/riscv/virt.c                     | 16 +++++++++++++++-
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 05fae82f1b..bb3dd34606 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI_GENERIC=y
 CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 05fae82f1b..bb3dd34606 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI_GENERIC=y
 CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e7f0716fb6..de6924e1c7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,6 +36,7 @@
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "chardev/char.h"
+#include "net/net.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "exec/address-spaces.h"
@@ -392,6 +393,8 @@ static void riscv_virt_board_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+    DeviceState *dev;
+    PCIBus *pci_bus;
     char *plic_hart_config;
     size_t plic_hart_config_len;
     int i;
@@ -506,13 +509,24 @@ static void riscv_virt_board_init(MachineState *machine)
             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
     }
 
-    gpex_pcie_init(system_memory,
+    dev = gpex_pcie_init(system_memory,
                          memmap[VIRT_PCIE_ECAM].base,
                          memmap[VIRT_PCIE_ECAM].size,
                          memmap[VIRT_PCIE_MMIO].base,
                          memmap[VIRT_PCIE_MMIO].size,
                          memmap[VIRT_PCIE_PIO].base,
                          DEVICE(s->plic), true);
+    pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+    for (i = 0; i < nb_nics; i++) {
+        NICInfo *nd = &nd_table[i];
+
+        if (!nd->model) {
+            nd->model = g_strdup("virtio");
+        }
+
+        pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+    }
 
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
-- 
2.19.1

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Logan Gunthorpe]

On 2018-11-21 10:03 a.m., Alistair Francis wrote:
> +    pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> +
> +    for (i = 0; i < nb_nics; i++) {
> +        NICInfo *nd = &nd_table[i];
> +
> +        if (!nd->model) {
> +            nd->model = g_strdup("virtio");
> +        }
> +
> +        pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
> +    }

I don't understand what this patch actually accomplishes. It doesn't
seem to affect my network devices when running QEMU. Can you provide a
commit message explaining this?

Thanks,

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:07 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
> On 2018-11-21 10:03 a.m., Alistair Francis wrote:
> > +    pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> > +
> > +    for (i = 0; i < nb_nics; i++) {
> > +        NICInfo *nd = &nd_table[i];
> > +
> > +        if (!nd->model) {
> > +            nd->model = g_strdup("virtio");
> > +        }
> > +
> > +        pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
> > +    }
>
> I don't understand what this patch actually accomplishes. It doesn't
> seem to affect my network devices when running QEMU. Can you provide a
> commit message explaining this?

Could you connect a PCIe networking device without this commit? This
is what the other architectures all do as well.

I'll rejig the commit message/title to make this clearer.

Alistair

>
> Thanks,
>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Logan Gunthorpe]

On 2018-11-21 11:34 a.m., Alistair Francis wrote:
>> I don't understand what this patch actually accomplishes. It doesn't
>> seem to affect my network devices when running QEMU. Can you provide a
>> commit message explaining this?
> 
> Could you connect a PCIe networking device without this commit? This
> is what the other architectures all do as well.

Yes, actually.

Other architectures doing something is never a sufficient justification
to make a change. I'm also not sure how virtio relates to this patch...

I'd say unless you know you're fixing something specific and can
describe it, you should drop this patch.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:12 AM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 11:34 a.m., Alistair Francis wrote:
> >> I don't understand what this patch actually accomplishes. It doesn't
> >> seem to affect my network devices when running QEMU. Can you provide a
> >> commit message explaining this?
> >
> > Could you connect a PCIe networking device without this commit? This
> > is what the other architectures all do as well.
>
> Yes, actually.
>
> Other architectures doing something is never a sufficient justification
> to make a change. I'm also not sure how virtio relates to this patch...
>
> I'd say unless you know you're fixing something specific and can
> describe it, you should drop this patch.

It is required for networking for PCIe devices. What PCIe device works
for you without this patch? Can you tell me your command line
arguments.

Alistair

>
> Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Logan Gunthorpe]

On 2018-11-21 2:55 p.m., Alistair Francis wrote:
> It is required for networking for PCIe devices. What PCIe device works
> for you without this patch? Can you tell me your command line
> arguments.

I can run it without that patch using a e1000e device and it works just
fine.

Command line:

$QEMU -s -nographic -machine virt -m 2G -kernel $BBL \
   -object rng-random,filename=/dev/urandom,id=rng0 \
   -append "console=hvc0 ro root=/dev/vda" \
   -device e1000e,netdev=net0 \
   -netdev user,id=net0 \
   -device virtio-rng-device,rng=rng0 \
   -device virtio-blk-device,drive=hd0 \
   -drive file=rootfs.img,format=raw,id=hd0 \
   -device nvme,drive=nvme0,serial=nvme0 \
   -drive file=nvme0.qcow2,if=none,id=nvme0

--

lspcirv-hfu-01:~#
00:00.0 Host bridge: Red Hat, Inc. QEMU PCIe Host bridge
00:01.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
Connection
00:02.0 Non-Volatile memory controller: Intel Corporation QEMU NVM
Express Controller (rev 02)
root@rv-hfu-01:~#

QEMU 3.0.92 monitor - type 'help' for more information
(qemu) info pci
  Bus  0, device   0, function 0:
    Host bridge: PCI device 1b36:0008
      PCI subsystem 1af4:1100
      id ""
  Bus  0, device   1, function 0:
    Ethernet controller: PCI device 8086:10d3
      PCI subsystem 8086:0000
      IRQ 11.
      BAR0: 32 bit memory at 0x40040000 [0x4005ffff].
      BAR1: 32 bit memory at 0x40060000 [0x4007ffff].
      BAR2: I/O at 0xffffffffffffffff [0x001e].
      BAR3: 32 bit memory at 0x40080000 [0x40083fff].
      BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe].
      id ""
  Bus  0, device   2, function 0:
    Class 0264: PCI device 8086:5845
      PCI subsystem 1af4:1100
      IRQ 9.
      BAR0: 64 bit memory at 0x40084000 [0x40085fff].
      id ""
(qemu)

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Alistair Francis]

On Wed, Nov 21, 2018 at 2:07 PM Logan Gunthorpe <logang@deltatee.com> wrote:
>
>
>
> On 2018-11-21 2:55 p.m., Alistair Francis wrote:
> > It is required for networking for PCIe devices. What PCIe device works
> > for you without this patch? Can you tell me your command line
> > arguments.
>
> I can run it without that patch using a e1000e device and it works just
> fine.
>
> Command line:
>
> $QEMU -s -nographic -machine virt -m 2G -kernel $BBL \
>    -object rng-random,filename=/dev/urandom,id=rng0 \
>    -append "console=hvc0 ro root=/dev/vda" \
>    -device e1000e,netdev=net0 \
>    -netdev user,id=net0 \
>    -device virtio-rng-device,rng=rng0 \
>    -device virtio-blk-device,drive=hd0 \
>    -drive file=rootfs.img,format=raw,id=hd0 \
>    -device nvme,drive=nvme0,serial=nvme0 \
>    -drive file=nvme0.qcow2,if=none,id=nvme0
>
> --
>
> lspcirv-hfu-01:~#
> 00:00.0 Host bridge: Red Hat, Inc. QEMU PCIe Host bridge
> 00:01.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
> 00:02.0 Non-Volatile memory controller: Intel Corporation QEMU NVM
> Express Controller (rev 02)
> root@rv-hfu-01:~#
>
> QEMU 3.0.92 monitor - type 'help' for more information
> (qemu) info pci
>   Bus  0, device   0, function 0:
>     Host bridge: PCI device 1b36:0008
>       PCI subsystem 1af4:1100
>       id ""
>   Bus  0, device   1, function 0:
>     Ethernet controller: PCI device 8086:10d3
>       PCI subsystem 8086:0000
>       IRQ 11.
>       BAR0: 32 bit memory at 0x40040000 [0x4005ffff].
>       BAR1: 32 bit memory at 0x40060000 [0x4007ffff].
>       BAR2: I/O at 0xffffffffffffffff [0x001e].
>       BAR3: 32 bit memory at 0x40080000 [0x40083fff].
>       BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe].
>       id ""
>   Bus  0, device   2, function 0:
>     Class 0264: PCI device 8086:5845
>       PCI subsystem 1af4:1100
>       IRQ 9.
>       BAR0: 64 bit memory at 0x40084000 [0x40085fff].
>       id ""
> (qemu)

and networking works?

Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Alistair Francis]

On Wed, Nov 21, 2018 at 2:11 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Nov 21, 2018 at 2:07 PM Logan Gunthorpe <logang@deltatee.com> wrote:
> >
> >
> >
> > On 2018-11-21 2:55 p.m., Alistair Francis wrote:
> > > It is required for networking for PCIe devices. What PCIe device works
> > > for you without this patch? Can you tell me your command line
> > > arguments.
> >
> > I can run it without that patch using a e1000e device and it works just
> > fine.
> >
> > Command line:
> >
> > $QEMU -s -nographic -machine virt -m 2G -kernel $BBL \
> >    -object rng-random,filename=/dev/urandom,id=rng0 \
> >    -append "console=hvc0 ro root=/dev/vda" \
> >    -device e1000e,netdev=net0 \
> >    -netdev user,id=net0 \
> >    -device virtio-rng-device,rng=rng0 \
> >    -device virtio-blk-device,drive=hd0 \
> >    -drive file=rootfs.img,format=raw,id=hd0 \
> >    -device nvme,drive=nvme0,serial=nvme0 \
> >    -drive file=nvme0.qcow2,if=none,id=nvme0
> >
> > --
> >
> > lspcirv-hfu-01:~#
> > 00:00.0 Host bridge: Red Hat, Inc. QEMU PCIe Host bridge
> > 00:01.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> > Connection
> > 00:02.0 Non-Volatile memory controller: Intel Corporation QEMU NVM
> > Express Controller (rev 02)
> > root@rv-hfu-01:~#
> >
> > QEMU 3.0.92 monitor - type 'help' for more information
> > (qemu) info pci
> >   Bus  0, device   0, function 0:
> >     Host bridge: PCI device 1b36:0008
> >       PCI subsystem 1af4:1100
> >       id ""
> >   Bus  0, device   1, function 0:
> >     Ethernet controller: PCI device 8086:10d3
> >       PCI subsystem 8086:0000
> >       IRQ 11.
> >       BAR0: 32 bit memory at 0x40040000 [0x4005ffff].
> >       BAR1: 32 bit memory at 0x40060000 [0x4007ffff].
> >       BAR2: I/O at 0xffffffffffffffff [0x001e].
> >       BAR3: 32 bit memory at 0x40080000 [0x40083fff].
> >       BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe].
> >       id ""
> >   Bus  0, device   2, function 0:
> >     Class 0264: PCI device 8086:5845
> >       PCI subsystem 1af4:1100
> >       IRQ 9.
> >       BAR0: 64 bit memory at 0x40084000 [0x40085fff].
> >       id ""
> > (qemu)
>
> and networking works?

Yep, it should. This is for the -nic option [1]. I misunderstood when
I was going through it.

We can drop this patch then.

1: https://github.com/qemu/qemu/commit/fea9b3ca9cc4685f89e0b929a61e51098fbb4f49

Alistair

>
> Alistair

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Logan Gunthorpe]

On 2018-11-21 3:14 p.m., Alistair Francis wrote:
>> and networking works?
> 
> Yep, it should. This is for the -nic option [1]. I misunderstood when
> I was going through it.
> 
> We can drop this patch then.
> 
> 1: https://github.com/qemu/qemu/commit/fea9b3ca9cc4685f89e0b929a61e51098fbb4f49

Ah, ok, that clears it up. You can drop it or keep it, but if you keep
it you should have a similar commit message.

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

[Logan Gunthorpe]

On 2018-11-21 3:16 p.m., Logan Gunthorpe wrote:
> 
> 
> On 2018-11-21 3:14 p.m., Alistair Francis wrote:
>>> and networking works?
>>
>> Yep, it should. This is for the -nic option [1]. I misunderstood when
>> I was going through it.
>>
>> We can drop this patch then.
>>
>> 1: https://github.com/qemu/qemu/commit/fea9b3ca9cc4685f89e0b929a61e51098fbb4f49
> 
> Ah, ok, that clears it up. You can drop it or keep it, but if you keep
> it you should have a similar commit message.

Though, if you choose to keep the patch, falling back to virtio as the
default NIC may not be the correct choice seeing the machine does not
have any virtio bus...

Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Andrea Bolognani]

On Wed, 2018-11-21 at 17:02 +0000, Alistair Francis wrote:
> V7:
>  - Fix the GPEX memory mapping thanks to Bin Meng
>  - Fix the interrupt mapping thanks to Logan Gunthorpe
> 
[...]
> 
> Alistair Francis (6):
>   hw/riscv/virt: Increase the number of interrupts
>   hw/riscv/virt: Adjust memory layout spacing
>   hw/riscv/virt: Connect the gpex PCIe
>   riscv: Enable VGA and PCIE_VGA
>   hw/riscv/sifive_u: Connect the Xilinx PCIe
>   hw/riscv/virt: Connect a VirtIO net PCIe device

Using QEMU master + these patches, libvirt master + my own patches,
a disk image from [1] and the bbl from [2], I was able to run a pure
PCI RISC-V guest, including connecting to it through ssh and
performing a system update using dnf; based on these results, the
series gets a big old

  Tested-by: Andrea Bolognani <abologna@redhat.com>


[1] https://fedora-riscv.tranquillity.se/koji/
    Unfortunately the site is broken at the moment :(
[2] https://fedorapeople.org/groups/risc-v/disk-images/
    PCI support is included in the bbl now! \o/
-- 
Andrea Bolognani / Red Hat / Virtualization

Re: [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Alistair Francis]

On Thu, Nov 22, 2018 at 2:59 AM Andrea Bolognani <abologna@redhat.com> wrote:
>
> On Wed, 2018-11-21 at 17:02 +0000, Alistair Francis wrote:
> > V7:
> >  - Fix the GPEX memory mapping thanks to Bin Meng
> >  - Fix the interrupt mapping thanks to Logan Gunthorpe
> >
> [...]
> >
> > Alistair Francis (6):
> >   hw/riscv/virt: Increase the number of interrupts
> >   hw/riscv/virt: Adjust memory layout spacing
> >   hw/riscv/virt: Connect the gpex PCIe
> >   riscv: Enable VGA and PCIE_VGA
> >   hw/riscv/sifive_u: Connect the Xilinx PCIe
> >   hw/riscv/virt: Connect a VirtIO net PCIe device
>
> Using QEMU master + these patches, libvirt master + my own patches,
> a disk image from [1] and the bbl from [2], I was able to run a pure
> PCI RISC-V guest, including connecting to it through ssh and
> performing a system update using dnf; based on these results, the
> series gets a big old
>
>   Tested-by: Andrea Bolognani <abologna@redhat.com>

Great! Thanks for testing.

Alistair

>
>
> [1] https://fedora-riscv.tranquillity.se/koji/
>     Unfortunately the site is broken at the moment :(
> [2] https://fedorapeople.org/groups/risc-v/disk-images/
>     PCI support is included in the bbl now! \o/
> --
> Andrea Bolognani / Red Hat / Virtualization
>

Re: [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Palmer Dabbelt]

On Thu, 22 Nov 2018 02:59:18 PST (-0800), abologna@redhat.com wrote:
> On Wed, 2018-11-21 at 17:02 +0000, Alistair Francis wrote:
>> V7:
>>  - Fix the GPEX memory mapping thanks to Bin Meng
>>  - Fix the interrupt mapping thanks to Logan Gunthorpe
>>
> [...]
>>
>> Alistair Francis (6):
>>   hw/riscv/virt: Increase the number of interrupts
>>   hw/riscv/virt: Adjust memory layout spacing
>>   hw/riscv/virt: Connect the gpex PCIe
>>   riscv: Enable VGA and PCIE_VGA
>>   hw/riscv/sifive_u: Connect the Xilinx PCIe
>>   hw/riscv/virt: Connect a VirtIO net PCIe device
>
> Using QEMU master + these patches, libvirt master + my own patches,
> a disk image from [1] and the bbl from [2], I was able to run a pure
> PCI RISC-V guest, including connecting to it through ssh and
> performing a system update using dnf; based on these results, the
> series gets a big old
>
>   Tested-by: Andrea Bolognani <abologna@redhat.com>
>
>
> [1] https://fedora-riscv.tranquillity.se/koji/
>     Unfortunately the site is broken at the moment :(

FWIW, I get my images from here

    https://fedorapeople.org/groups/risc-v/disk-images/

which is linked to from the Fedora wiki

    https://fedoraproject.org/wiki/Architectures/RISC-V/Disk_images

the stage4 there is quite old (April, 2018), is yours newer?  I'm having some 
problems updating my disk image and since I'm not a Fedora user I have no idea 
what's going on.

> [2] https://fedorapeople.org/groups/risc-v/disk-images/
>     PCI support is included in the bbl now! \o/

Great!  I've yet to figure out how to get all the PCI stuff working, but I was 
trying to go with a virgl-based GPU which I suspect is broken for other 
reasons.  What sort of devices did you attach?

Re: [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Guenter Roeck]

On Mon, Nov 26, 2018 at 11:34:58AM -0800, Palmer Dabbelt wrote:
> On Thu, 22 Nov 2018 02:59:18 PST (-0800), abologna@redhat.com wrote:
> > On Wed, 2018-11-21 at 17:02 +0000, Alistair Francis wrote:
> >> V7:
> >>  - Fix the GPEX memory mapping thanks to Bin Meng
> >>  - Fix the interrupt mapping thanks to Logan Gunthorpe
> >>
> > [...]
> >>
> >> Alistair Francis (6):
> >>   hw/riscv/virt: Increase the number of interrupts
> >>   hw/riscv/virt: Adjust memory layout spacing
> >>   hw/riscv/virt: Connect the gpex PCIe
> >>   riscv: Enable VGA and PCIE_VGA
> >>   hw/riscv/sifive_u: Connect the Xilinx PCIe
> >>   hw/riscv/virt: Connect a VirtIO net PCIe device
> >
> > Using QEMU master + these patches, libvirt master + my own patches,
> > a disk image from [1] and the bbl from [2], I was able to run a pure
> > PCI RISC-V guest, including connecting to it through ssh and
> > performing a system update using dnf; based on these results, the
> > series gets a big old
> >
> >   Tested-by: Andrea Bolognani <abologna@redhat.com>
> >
> >
> > [1] https://fedora-riscv.tranquillity.se/koji/
> >     Unfortunately the site is broken at the moment :(
> 
> FWIW, I get my images from here
> 
>     https://fedorapeople.org/groups/risc-v/disk-images/
> 
> which is linked to from the Fedora wiki
> 
>     https://fedoraproject.org/wiki/Architectures/RISC-V/Disk_images
> 
> the stage4 there is quite old (April, 2018), is yours newer?  I'm having some 
> problems updating my disk image and since I'm not a Fedora user I have no idea 
> what's going on.
> 
> > [2] https://fedorapeople.org/groups/risc-v/disk-images/
> >     PCI support is included in the bbl now! \o/
> 
> Great!  I've yet to figure out how to get all the PCI stuff working, but I was 
> trying to go with a virgl-based GPU which I suspect is broken for other 
> reasons.  What sort of devices did you attach?

FWIW, here is my list of tests.

Building riscv:virt:defconfig:initrd ... running ....... passed
Building riscv:virt:defconfig:virtio-blk:rootfs ... running ........ passed
Building riscv:virt:defconfig:virtio:rootfs ... running ........ passed
Building riscv:virt:defconfig:virtio-pci:rootfs ... running ........ passed
Building riscv:virt:defconfig:mmc:rootfs ... running ........ passed
Building riscv:virt:defconfig:nvme:rootfs ... running ........ passed
Building riscv:virt:defconfig:usb-ohci:rootfs ... running ........ passed
Building riscv:virt:defconfig:usb-ehci:rootfs ... running ........ passed
Building riscv:virt:defconfig:usb-xhci:rootfs ... running ......... passed
Building riscv:virt:defconfig:usb-uas-ehci:rootfs ... running ......... passed
Building riscv:virt:defconfig:usb-uas-xhci:rootfs ... running ......... passed
Building riscv:virt:defconfig:scsi[53C810]:rootfs ... running ........... passed
Building riscv:virt:defconfig:scsi[53C895A]:rootfs ... running ......... passed
Building riscv:virt:defconfig:scsi[AM53C974]:rootfs ... skipped
Building riscv:virt:defconfig:scsi[DC395]:rootfs ... skipped
Building riscv:virt:defconfig:scsi[MEGASAS]:rootfs ... running ......... passed
Building riscv:virt:defconfig:scsi[MEGASAS2]:rootfs ... running ........ passed
Building riscv:virt:defconfig:scsi[FUSION]:rootfs ... running ....... passed
Building riscv:virt:defconfig:scsi[virtio]:rootfs ... running ....... passed
Building riscv:virt:defconfig:scsi[virtio-pci]:rootfs ... running ........ passed

The skipped tests work as well, but the emulation is flaky and fails once
in a while. This is obviously with usb enabled.

Guenter

Re: [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V

[Andrea Bolognani]

On Mon, 2018-11-26 at 11:34 -0800, Palmer Dabbelt wrote:
> FWIW, I get my images from here
> 
>     https://fedorapeople.org/groups/risc-v/disk-images/
> 
> which is linked to from the Fedora wiki
> 
>     https://fedoraproject.org/wiki/Architectures/RISC-V/Disk_images
> 
> the stage4 there is quite old (April, 2018), is yours newer?  I'm having some 
> problems updating my disk image and since I'm not a Fedora user I have no idea 
> what's going on.

Yeah, we have nightly built images now - they come in several
flavors, even!

  http://185.97.32.145/koji/tasks?state=closed&view=flat&method=createAppliance&order=-id

Note that there are some issues with the server configuration and
the HSTS preload list shipped with browsers not playing nice with
each other, so you'll have to tweak URLs a bit before you can
actually download images, basically

  s,https://fedora-riscv.tranquillity.se,http://185.97.32.145,

I wonder if it even makes sense to keep the old stage4 images
around... And someone should definitely sweep through the wiki
and make sure we don't point to obsolete information and all URLs
are up to date. Maybe I should create that Fedora Account after
all O:-)

> > [2] https://fedorapeople.org/groups/risc-v/disk-images/
> >     PCI support is included in the bbl now! \o/
> 
> Great!  I've yet to figure out how to get all the PCI stuff working, but I was 
> trying to go with a virgl-based GPU which I suspect is broken for other 
> reasons.  What sort of devices did you attach?

I just tried today, and virtio-gpu doesn't work for me either:
during boot I get

  [drm] radeon kernel modesetting enabled.
  [drm] pci: virtio-gpu-pci detected at 0000:00:05.0
  [drm] virgl 3d acceleration not supported by host
  [TTM] Zone  kernel: Available graphics memory: 993416 kiB
  [TTM] Initializing pool allocator
  [TTM] Initializing DMA pool allocator
  [drm] number of scanouts: 1
  [drm] number of cap sets: 0
  ------------[ cut here ]------------
  WARNING: CPU: 3 PID: 1 at lib/scatterlist.c:275 __sg_alloc_table+0xba/0xbe
  Modules linked in:
  CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.19.0-rc8 #1
  Call Trace:
  [<ffffffe0000383ec>] walk_stackframe+0x0/0xa0
  [<ffffffe000038588>] show_stack+0x2a/0x34
  [<ffffffe0006b12b2>] dump_stack+0x62/0x7c
  [<ffffffe00003c498>] __warn+0xd2/0xe4
  [<ffffffe00003c544>] warn_slowpath_null+0x30/0x3e
  [<ffffffe0002a1646>] __sg_alloc_table+0xba/0xbe
  [<ffffffe0002a18c8>] sg_alloc_table+0x28/0xa6
  [<ffffffe0002a1a1a>] __sg_alloc_table_from_pages+0xd4/0x1da
  [<ffffffe0002a1b30>] sg_alloc_table_from_pages+0x10/0x18
  [<ffffffe00042c87c>] virtio_gpu_object_get_sg_table+0x90/0xa6
  [<ffffffe00042bdfc>] virtio_gpu_object_attach+0x12c/0x14c
  [<ffffffe00042a1aa>] virtio_gpufb_create+0xe4/0x1c0
  [<ffffffe0003345f2>] __drm_fb_helper_initial_config_and_unlock+0x198/0x334
  [<ffffffe000334c5a>] drm_fb_helper_initial_config+0x2e/0x3a
  [<ffffffe00042a3f6>] virtio_gpu_fbdev_init+0xa6/0xce
  [<ffffffe000429556>] virtio_gpu_driver_load+0x36e/0x3be
  [<ffffffe00033a932>] drm_dev_register+0xfe/0x162
  [<ffffffe000429968>] drm_virtio_init+0x48/0x158
  [<ffffffe000429164>] virtio_gpu_probe+0x32/0x40
  [<ffffffe0002f7e58>] virtio_dev_probe+0x10e/0x196
  [<ffffffe00043546c>] really_probe+0x17e/0x1ea
  [<ffffffe000435654>] driver_probe_device+0x7a/0x90
  [<ffffffe000435702>] __driver_attach+0x98/0x9a
  [<ffffffe000433bc2>] bus_for_each_dev+0x4a/0x72
  [<ffffffe000434f28>] driver_attach+0x1a/0x22
  [<ffffffe000434b06>] bus_add_driver+0x156/0x1b8
  [<ffffffe000435c88>] driver_register+0x3a/0xd0
  [<ffffffe0002f7f00>] register_virtio_driver+0x20/0x2e
  [<ffffffe000012d92>] virtio_gpu_driver_init+0x18/0x20
  [<ffffffe00003664a>] do_one_initcall+0x2c/0x10a
  [<ffffffe000000a90>] kernel_init_freeable+0x11e/0x1ae
  [<ffffffe0006c2304>] kernel_init+0x12/0xf0
  [<ffffffe000037472>] ret_from_exception+0x0/0xc
  ---[ end trace 161c50bff518fcd6 ]---
  [drm] Initialized virtio_gpu 0.0.1 0 for virtio5 on minor 0

and the graphical console is not initialized.

The libvirt guest XML I'm using is

  <domain type='qemu'>
    <name>riscv</name>
    <memory unit='GiB'>2</memory>
    <vcpu>4</vcpu>
    <os>
      <type arch='riscv64' machine='virt'>hvm</type>
      <kernel>/var/lib/libvirt/images/riscv.bbl</kernel>
      <cmdline>root=/dev/vda1</cmdline>
    </os>
    <devices>
      <emulator>/usr/bin/qemu-system-riscv64</emulator>
      <disk type='file' device='disk'>
        <driver name='qemu' type='raw'/>
        <source file='/var/lib/libvirt/images/riscv.raw'/>
        <target dev='vda' bus='virtio'/>
        <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0'/>
      </disk>
      <controller type='pci' model='pcie-root'/>
      <controller type='virtio-serial'>
        <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/>
      </controller>
      <interface type='network'>
        <source network='default'/>
        <model type='virtio'/>
        <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x0'/>
      </interface>
      <serial type='pty'/>
      <channel type='unix'>
        <target type='virtio' name='org.qemu.guest_agent.0'/>
      </channel>
      <graphics type='spice'/>
      <video>
        <model type='virtio'/>
        <address type='pci' domain='0x0000' bus='0x00' slot='0x04' function='0x0'/>
      </video>
      <memballoon model='virtio'>
        <address type='pci' domain='0x0000' bus='0x00' slot='0x05' function='0x0'/>
      </memballoon>
      <rng model='virtio'>
        <backend model='random'>/dev/urandom</backend>
        <address type='pci' domain='0x0000' bus='0x00' slot='0x06' function='0x0'/>
      </rng>
    </devices>
  </domain>

but you're going to need a libvirt built from

  https://github.com/andreabolognani/libvirt/tree/riscv-pci

in order to actually use it.

I think the BBL I'm using doesn't have ballooning support, and I
haven't bothered trying it either, but as reported earlier everything
else (disk, networking, RNG, shutdown via qemu-guest-agent) works
just fine.

-- 
Andrea Bolognani / Red Hat / Virtualization