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From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	Wei Huang <wei@redhat.com>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Michael Spradling <mspradli@codeaurora.org>,
	Digant Desai <digantd@codeaurora.org>,
	Aaron Lindsay <aaron@os.amperecomputing.com>
Subject: [Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3
Date: Wed, 5 Dec 2018 13:43:04 +0000	[thread overview]
Message-ID: <20181205134243.4791-1-aaron@os.amperecomputing.com> (raw)

The ARM PMU implementation currently contains a basic cycle counter, but
it is often useful to gather counts of other events, filter them based
on execution mode, and/or be notified on counter overflow. These patches
flesh out the implementations of various PMU registers including
PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent
arbitrary counter types, implement mode filtering, send interrupts on
counter overflow, and add instruction, cycle, and software increment
events.

Since v8 [1] I have made the following changes:
* Simplified if statements and corrected overflow bit clearing logic in
  counter overflow patch based on Richard's review
* Added FIELDs for ARMv8.1 PMUv3 variant and guard the definition of
  PMCEID2 and PMCEID3 based on ID_DFR0.PerfMon
* Added/fixed up a couple comments

[1] - https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg04037.html

Aaron Lindsay (14):
  migration: Add post_save function to VMStateDescription
  target/arm: Reorganize PMCCNTR accesses
  target/arm: Swap PMU values before/after migrations
  target/arm: Filter cycle counter based on PMCCFILTR_EL0
  target/arm: Allow AArch32 access for PMCCFILTR
  target/arm: Implement PMOVSSET
  target/arm: Define FIELDs for ID_DFR0
  target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
  target/arm: Add array for supported PMU events, generate
    PMCEID[01]_EL0
  target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
  target/arm: PMU: Add instruction and cycle events
  target/arm: PMU: Set PMCR.N to 4
  target/arm: Implement PMSWINC
  target/arm: Send interrupts on PMU counter overflow

 docs/devel/migration.rst    |   9 +-
 include/migration/vmstate.h |   1 +
 migration/vmstate.c         |  13 +-
 target/arm/cpu.c            |  28 +-
 target/arm/cpu.h            |  79 +++-
 target/arm/cpu64.c          |   4 -
 target/arm/helper.c         | 807 ++++++++++++++++++++++++++++++++----
 target/arm/machine.c        |  24 ++
 8 files changed, 860 insertions(+), 105 deletions(-)

-- 
2.19.1

             reply	other threads:[~2018-12-05 13:43 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-05 13:43 Aaron Lindsay [this message]
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 01/14] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 03/14] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 06/14] target/arm: Implement PMOVSSET Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0 Aaron Lindsay
2018-12-06 15:56   ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-12-05 15:32   ` Aaron Lindsay
2018-12-06 15:59     ` Peter Maydell
2018-12-07 18:00     ` Richard Henderson
2018-12-09 21:58       ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 13/14] target/arm: Implement PMSWINC Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-12-06 16:03   ` Peter Maydell
2018-12-11 14:46     ` Aaron Lindsay

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