From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair.francis@xilinx.com>,
Wei Huang <wei@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
Michael Spradling <mspradli@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>,
Aaron Lindsay <aaron@os.amperecomputing.com>
Subject: [Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0
Date: Wed, 5 Dec 2018 13:43:21 +0000 [thread overview]
Message-ID: <20181205134243.4791-8-aaron@os.amperecomputing.com> (raw)
In-Reply-To: <20181205134243.4791-1-aaron@os.amperecomputing.com>
This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
---
target/arm/cpu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 627e5c1995..304e6e47b3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1586,6 +1586,14 @@ FIELD(ID_AA64PFR0, GIC, 24, 4)
FIELD(ID_AA64PFR0, RAS, 28, 4)
FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_DFR0, COPDBG, 0, 4)
+FIELD(ID_DFR0, COPSDBG, 4, 4)
+FIELD(ID_DFR0, MMAPDBG, 8, 4)
+FIELD(ID_DFR0, COPTRC, 12, 4)
+FIELD(ID_DFR0, MMAPTRC, 16, 4)
+FIELD(ID_DFR0, MPROFDBG, 20, 4)
+FIELD(ID_DFR0, PERFMON, 24, 4)
+
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
/* If adding a feature bit which corresponds to a Linux ELF
--
2.19.1
next prev parent reply other threads:[~2018-12-05 13:44 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-05 13:43 [Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 01/14] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 03/14] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 06/14] target/arm: Implement PMOVSSET Aaron Lindsay
2018-12-05 13:43 ` Aaron Lindsay [this message]
2018-12-06 15:56 ` [Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0 Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-12-05 15:32 ` Aaron Lindsay
2018-12-06 15:59 ` Peter Maydell
2018-12-07 18:00 ` Richard Henderson
2018-12-09 21:58 ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 13/14] target/arm: Implement PMSWINC Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-12-06 16:03 ` Peter Maydell
2018-12-11 14:46 ` Aaron Lindsay
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