qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com
Subject: [Qemu-devel] [PATCH 26/26] target/arm: Tidy TBI handling in gen_a64_set_pc
Date: Fri,  7 Dec 2018 04:36:31 -0600	[thread overview]
Message-ID: <20181207103631.28193-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org>

We can perform this with fewer operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 65 ++++++++++++++------------------------
 1 file changed, 23 insertions(+), 42 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 99e1405dff..15080cbb3c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val)
 /* Load the PC from a generic TCG variable.
  *
  * If address tagging is enabled via the TCR TBI bits, then loading
- * an address into the PC will clear out any tag in the it:
+ * an address into the PC will clear out any tag in it:
  *  + for EL2 and EL3 there is only one TBI bit, and if it is set
  *    then the address is zero-extended, clearing bits [63:56]
  *  + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
@@ -276,56 +276,37 @@ void gen_a64_set_pc_im(uint64_t val)
  */
 static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
 {
+    bool tbi0 = s->tbi0, tbi1 = s->tbi1;
 
     if (s->current_el <= 1) {
-        /* Test if NEITHER or BOTH TBI values are set.  If so, no need to
-         * examine bit 55 of address, can just generate code.
-         * If mixed, then test via generated code
-         */
-        if (s->tbi0 && s->tbi1) {
-            TCGv_i64 tmp_reg = tcg_temp_new_i64();
-            /* Both bits set, sign extension from bit 55 into [63:56] will
-             * cover both cases
-             */
-            tcg_gen_shli_i64(tmp_reg, src, 8);
-            tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
-            tcg_temp_free_i64(tmp_reg);
-        } else if (!s->tbi0 && !s->tbi1) {
-            /* Neither bit set, just load it as-is */
-            tcg_gen_mov_i64(cpu_pc, src);
-        } else {
-            TCGv_i64 tcg_tmpval = tcg_temp_new_i64();
-            TCGv_i64 tcg_bit55  = tcg_temp_new_i64();
-            TCGv_i64 tcg_zero   = tcg_const_i64(0);
+        if (tbi0 || tbi1) {
+            /* Sign-extend from bit 55.  */
+            tcg_gen_sextract_i64(cpu_pc, src, 0, 56);
 
-            tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
+            if (tbi0 != tbi1) {
+                TCGv_i64 tcg_zero = tcg_const_i64(0);
 
-            if (s->tbi0) {
-                /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
-                tcg_gen_andi_i64(tcg_tmpval, src,
-                                 0x00FFFFFFFFFFFFFFull);
-                tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero,
-                                    tcg_tmpval, src);
-            } else {
-                /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
-                tcg_gen_ori_i64(tcg_tmpval, src,
-                                0xFF00000000000000ull);
-                tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero,
-                                    tcg_tmpval, src);
+                /*
+                 * The two TBI bits differ.
+                 * If tbi0, then !tbi1: only use the extension if positive.
+                 * if !tbi0, then tbi1: only use the extension if negative.
+                 */
+                tcg_gen_movcond_i64(tbi0 ? TCG_COND_GE : TCG_COND_LT,
+                                    cpu_pc, cpu_pc, tcg_zero, cpu_pc, src);
+                tcg_temp_free_i64(tcg_zero);
             }
-            tcg_temp_free_i64(tcg_zero);
-            tcg_temp_free_i64(tcg_bit55);
-            tcg_temp_free_i64(tcg_tmpval);
+            return;
         }
-    } else {  /* EL > 1 */
-        if (s->tbi0) {
+    } else {
+        if (tbi0) {
             /* Force tag byte to all zero */
-            tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
-        } else {
-            /* Load unmodified address */
-            tcg_gen_mov_i64(cpu_pc, src);
+            tcg_gen_extract_i64(cpu_pc, src, 0, 56);
+            return;
         }
     }
+
+    /* Load unmodified address */
+    tcg_gen_mov_i64(cpu_pc, src);
 }
 
 typedef struct DisasCompare64 {
-- 
2.17.2

      parent reply	other threads:[~2018-12-07 10:37 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-07 10:36 [Qemu-devel] [PATCH 00/26] target/arm: Implement ARMv8.3-PAuth Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 01/26] target/arm: Add state for the ARMv8.3-PAuth extension Richard Henderson
2018-12-11 14:50   ` Peter Maydell
2018-12-11 18:07     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 02/26] target/arm: Add SCTLR bits through ARMv8.5 Richard Henderson
2018-12-11 15:18   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 03/26] target/arm: Add PAuth active bit to tbflags Richard Henderson
2018-12-11 15:23   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 04/26] target/arm: Add PAuth helpers Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 05/26] target/arm: Decode PAuth within system hint space Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 06/26] target/arm: Rearrange decode in disas_data_proc_1src Richard Henderson
2018-12-11 15:29   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 07/26] target/arm: Decode PAuth within disas_data_proc_1src Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 08/26] target/arm: Decode PAuth within disas_data_proc_2src Richard Henderson
2018-12-11 15:31   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 09/26] target/arm: Move helper_exception_return to helper-a64.c Richard Henderson
2018-12-11 15:33   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 10/26] target/arm: Add new_pc argument to helper_exception_return Richard Henderson
2018-12-11 15:34   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 11/26] target/arm: Rearrange decode in disas_uncond_b_reg Richard Henderson
2018-12-11 15:40   ` Peter Maydell
2018-12-12 19:20     ` Richard Henderson
2018-12-12 21:18       ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 12/26] target/arm: Decode PAuth within disas_uncond_b_reg Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 13/26] target/arm: Decode Load/store register (pac) Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 14/26] target/arm: Move cpu_mmu_index out of line Richard Henderson
2018-12-11 15:41   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 15/26] target/arm: Introduce arm_mmu_idx Richard Henderson
2018-12-11 15:43   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 16/26] target/arm: Create ARMVAParameters and helpers Richard Henderson
2018-12-11 16:40   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for setting tbflags Richard Henderson
2018-12-11 16:52   ` Peter Maydell
2018-12-11 18:21     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 18/26] target/arm: Export aa64_va_parameters to internals.h Richard Henderson
2018-12-11 16:53   ` Peter Maydell
2018-12-11 18:23     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 19/26] target/arm: Implement pauth_strip Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 20/26] target/arm: Implement pauth_auth Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 21/26] target/arm: Implement pauth_addpac Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 22/26] target/arm: Implement pauth_computepac Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 23/26] target/arm: Add PAuth system registers Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 24/26] target/arm: Enable PAuth for user-only -cpu max Richard Henderson
2018-12-11 15:45   ` Peter Maydell
2018-12-11 18:24     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 25/26] target/arm: Enable PAuth for user-only, part 2 Richard Henderson
2018-12-07 10:36 ` Richard Henderson [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181207103631.28193-27-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=ramana.radhakrishnan@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).