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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com
Subject: [Qemu-devel] [PATCH 05/26] target/arm: Decode PAuth within system hint space
Date: Fri,  7 Dec 2018 04:36:10 -0600	[thread overview]
Message-ID: <20181207103631.28193-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++-----
 1 file changed, 81 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7c1cc1ce8e..0df344f9e8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t insn,
     }
 
     switch (selector) {
-    case 0: /* NOP */
-        return;
-    case 3: /* WFI */
+    case 000: /* NOP */
+        break;
+    case 003: /* WFI */
         s->base.is_jmp = DISAS_WFI;
-        return;
+        break;
+    case 001: /* YIELD */
         /* When running in MTTCG we don't generate jumps to the yield and
          * WFE helpers as it won't affect the scheduling of other vCPUs.
          * If we wanted to more completely model WFE/SEV so we don't busy
          * spin unnecessarily we would need to do something more involved.
          */
-    case 1: /* YIELD */
         if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
             s->base.is_jmp = DISAS_YIELD;
         }
-        return;
-    case 2: /* WFE */
+        break;
+    case 002: /* WFE */
         if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
             s->base.is_jmp = DISAS_WFE;
         }
-        return;
-    case 4: /* SEV */
-    case 5: /* SEVL */
+        break;
+    case 004: /* SEV */
+    case 005: /* SEVL */
         /* we treat all as NOP at least for now */
-        return;
+        break;
+    case 007: /* XPACLRI */
+        if (s->pauth_active) {
+            gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
+        }
+        break;
+    case 010: /* PACIA1716 */
+        if (s->pauth_active) {
+            gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 012: /* PACIB1716 */
+        if (s->pauth_active) {
+            gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 014: /* AUTIA1716 */
+        if (s->pauth_active) {
+            gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 016: /* AUTIB1716 */
+        if (s->pauth_active) {
+            gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 030: /* PACIAZ */
+        if (s->pauth_active) {
+            gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
+                                new_tmp_a64_zero(s));
+        }
+        break;
+    case 031: /* PACIASP */
+        if (s->pauth_active) {
+            gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
+    case 032: /* PACIBZ */
+        if (s->pauth_active) {
+            gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30],
+                                new_tmp_a64_zero(s));
+        }
+        break;
+    case 033: /* PACIBSP */
+        if (s->pauth_active) {
+            gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
+    case 034: /* AUTIAZ */
+        if (s->pauth_active) {
+            gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30],
+                              new_tmp_a64_zero(s));
+        }
+        break;
+    case 035: /* AUTIASP */
+        if (s->pauth_active) {
+            gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
+    case 036: /* AUTIBZ */
+        if (s->pauth_active) {
+            gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30],
+                              new_tmp_a64_zero(s));
+        }
+        break;
+    case 037: /* AUTIBSP */
+        if (s->pauth_active) {
+            gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
     default:
         /* default specified as NOP equivalent */
-        return;
+        break;
     }
 }
 
-- 
2.17.2

  parent reply	other threads:[~2018-12-07 10:36 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-07 10:36 [Qemu-devel] [PATCH 00/26] target/arm: Implement ARMv8.3-PAuth Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 01/26] target/arm: Add state for the ARMv8.3-PAuth extension Richard Henderson
2018-12-11 14:50   ` Peter Maydell
2018-12-11 18:07     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 02/26] target/arm: Add SCTLR bits through ARMv8.5 Richard Henderson
2018-12-11 15:18   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 03/26] target/arm: Add PAuth active bit to tbflags Richard Henderson
2018-12-11 15:23   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 04/26] target/arm: Add PAuth helpers Richard Henderson
2018-12-07 10:36 ` Richard Henderson [this message]
2018-12-07 10:36 ` [Qemu-devel] [PATCH 06/26] target/arm: Rearrange decode in disas_data_proc_1src Richard Henderson
2018-12-11 15:29   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 07/26] target/arm: Decode PAuth within disas_data_proc_1src Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 08/26] target/arm: Decode PAuth within disas_data_proc_2src Richard Henderson
2018-12-11 15:31   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 09/26] target/arm: Move helper_exception_return to helper-a64.c Richard Henderson
2018-12-11 15:33   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 10/26] target/arm: Add new_pc argument to helper_exception_return Richard Henderson
2018-12-11 15:34   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 11/26] target/arm: Rearrange decode in disas_uncond_b_reg Richard Henderson
2018-12-11 15:40   ` Peter Maydell
2018-12-12 19:20     ` Richard Henderson
2018-12-12 21:18       ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 12/26] target/arm: Decode PAuth within disas_uncond_b_reg Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 13/26] target/arm: Decode Load/store register (pac) Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 14/26] target/arm: Move cpu_mmu_index out of line Richard Henderson
2018-12-11 15:41   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 15/26] target/arm: Introduce arm_mmu_idx Richard Henderson
2018-12-11 15:43   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 16/26] target/arm: Create ARMVAParameters and helpers Richard Henderson
2018-12-11 16:40   ` Peter Maydell
2018-12-07 10:36 ` [Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for setting tbflags Richard Henderson
2018-12-11 16:52   ` Peter Maydell
2018-12-11 18:21     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 18/26] target/arm: Export aa64_va_parameters to internals.h Richard Henderson
2018-12-11 16:53   ` Peter Maydell
2018-12-11 18:23     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 19/26] target/arm: Implement pauth_strip Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 20/26] target/arm: Implement pauth_auth Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 21/26] target/arm: Implement pauth_addpac Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 22/26] target/arm: Implement pauth_computepac Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 23/26] target/arm: Add PAuth system registers Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 24/26] target/arm: Enable PAuth for user-only -cpu max Richard Henderson
2018-12-11 15:45   ` Peter Maydell
2018-12-11 18:24     ` Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 25/26] target/arm: Enable PAuth for user-only, part 2 Richard Henderson
2018-12-07 10:36 ` [Qemu-devel] [PATCH 26/26] target/arm: Tidy TBI handling in gen_a64_set_pc Richard Henderson

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