From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: [Qemu-devel] [PATCH v7 03/19] ppc/xive: introduce a simplified XIVE presenter
Date: Tue, 11 Dec 2018 12:37:10 +1100 [thread overview]
Message-ID: <20181211013710.GC4261@umbus.fritz.box> (raw)
In-Reply-To: <157aa1c9-20a6-e177-eac7-f47f40188df3@kaod.org>
[-- Attachment #1: Type: text/plain, Size: 2419 bytes --]
On Mon, Dec 10, 2018 at 08:15:40AM +0100, Cédric Le Goater wrote:
> On 12/10/18 5:27 AM, David Gibson wrote:
> > On Sun, Dec 09, 2018 at 08:45:54PM +0100, Cédric Le Goater wrote:
> >> The last sub-engine of the XIVE architecture is the Interrupt
> >> Virtualization Presentation Engine (IVPE). On HW, the IVRE and the
> >> IVPE share elements, the Power Bus interface (CQ), the routing table
> >> descriptors, and they can be combined in the same HW logic. We do the
> >> same in QEMU and combine both engines in the XiveRouter for
> >> simplicity.
> >>
> >> When the IVRE has completed its job of matching an event source with a
> >> Notification Virtual Target (NVT) to notify, it forwards the event
> >> notification to the IVPE sub-engine. The IVPE scans the thread
> >> interrupt contexts of the Notification Virtual Targets (NVT)
> >> dispatched on the HW processor threads and if a match is found, it
> >> signals the thread. If not, the IVPE escalates the notification to
> >> some other targets and records the notification in a backlog queue.
> >>
> >> The IVPE maintains the thread interrupt context state for each of its
> >> NVTs not dispatched on HW processor threads in the Notification
> >> Virtual Target table (NVTT).
> >>
> >> The model currently only supports single NVT notifications.
> >>
> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >
> > Applied.
> >
> > I think the tctx_word2() should have the byteswap, rather than having
> > it in the callers, but that can be fixed later.
>
> I thought it was better to explicitly show in the code where the
> byteswaps were needed. Anyway, this is very localized, so, yes,
> we can change it later on.
To clarify my thinking here; the important thing is not knowing where
the byteswaps are, but being able to tell as easily as possible what
endianness a given piece of data is right now.
The convention I'm aiming for here - which is one I try to use most
places is that structures - at least structures which map to specific
in-memory things - are in the required endianness for that stuff in
memory. However bare integers - uint32_t or uint64_t or whatever -
are, well, numbers, in native endian.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2018-12-11 1:37 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-09 19:45 [Qemu-devel] [PATCH v7 00/19] ppc: support for the XIVE interrupt controller (POWER9) Cédric Le Goater
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 01/19] ppc/xive: add support for the END Event State Buffers Cédric Le Goater
2018-12-10 4:16 ` David Gibson
2018-12-10 7:11 ` Cédric Le Goater
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 02/19] ppc/xive: introduce the XIVE interrupt thread context Cédric Le Goater
2018-12-10 4:19 ` David Gibson
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 03/19] ppc/xive: introduce a simplified XIVE presenter Cédric Le Goater
2018-12-10 4:27 ` David Gibson
2018-12-10 7:15 ` Cédric Le Goater
2018-12-11 1:37 ` David Gibson [this message]
2018-12-11 10:43 ` Cédric Le Goater
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 04/19] ppc/xive: notify the CPU when the interrupt priority is more privileged Cédric Le Goater
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 05/19] spapr/xive: introduce a XIVE interrupt controller Cédric Le Goater
2018-12-10 4:36 ` David Gibson
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 06/19] spapr/xive: use the VCPU id as a NVT identifier Cédric Le Goater
2018-12-10 4:42 ` David Gibson
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 07/19] spapr: introduce a new machine IRQ backend for XIVE Cédric Le Goater
2018-12-10 4:45 ` David Gibson
2018-12-09 19:45 ` [Qemu-devel] [PATCH v7 08/19] spapr: add hcalls support for the XIVE exploitation interrupt mode Cédric Le Goater
2018-12-10 6:34 ` David Gibson
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 09/19] spapr: add device tree support for the XIVE exploitation mode Cédric Le Goater
2018-12-10 6:39 ` David Gibson
2018-12-10 7:53 ` Cédric Le Goater
2018-12-11 0:38 ` David Gibson
2018-12-11 9:06 ` Cédric Le Goater
2018-12-12 0:19 ` David Gibson
2018-12-12 7:37 ` Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 10/19] spapr: allocate the interrupt thread context under the CPU core Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 11/19] spapr: extend the sPAPR IRQ backend for XICS migration Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 12/19] spapr: add a 'reset' method to the sPAPR IRQ backend Cédric Le Goater
2018-12-10 6:42 ` David Gibson
2018-12-10 7:30 ` Cédric Le Goater
2018-12-11 10:55 ` Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 13/19] spapr: add an extra OV5 field " Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 14/19] spapr: set the interrupt presenter at reset Cédric Le Goater
2018-12-11 1:46 ` David Gibson
2018-12-11 10:58 ` Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 15/19] spapr/xive: enable XIVE MMIOs " Cédric Le Goater
2018-12-11 1:47 ` David Gibson
2018-12-11 10:14 ` Cédric Le Goater
2018-12-12 0:32 ` David Gibson
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 16/19] spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS Cédric Le Goater
2018-12-11 2:03 ` David Gibson
2018-12-11 10:19 ` Cédric Le Goater
2018-12-12 0:54 ` David Gibson
2018-12-12 9:13 ` Cédric Le Goater
2018-12-15 8:09 ` David Gibson
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 17/19] spapr: Add a pseries-4.0 machine type Cédric Le Goater
2018-12-09 22:05 ` Benjamin Herrenschmidt
2018-12-10 3:41 ` David Gibson
2018-12-10 7:09 ` Cédric Le Goater
2018-12-10 6:45 ` David Gibson
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 18/19] spapr: add a 'pseries-4.0-xive' " Cédric Le Goater
2018-12-10 22:17 ` Cédric Le Goater
2018-12-11 2:06 ` David Gibson
2018-12-11 10:42 ` Cédric Le Goater
2018-12-11 16:44 ` Cédric Le Goater
2018-12-15 8:03 ` David Gibson
2018-12-12 0:34 ` David Gibson
2018-12-12 7:26 ` Cédric Le Goater
2018-12-09 19:46 ` [Qemu-devel] [PATCH v7 19/19] spapr: add a 'pseries-4.0-dual' " Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181211013710.GC4261@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=benh@kernel.crashing.org \
--cc=clg@kaod.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).