From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
Alistair Francis <alistair.francis@xilinx.com>,
Wei Huang <wei@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>,
Michael Spradling <mspradli@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>,
Aaron Lindsay <alindsay@codeaurora.org>
Subject: Re: [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow
Date: Tue, 11 Dec 2018 14:46:55 +0000 [thread overview]
Message-ID: <20181211144648.GJ5549@quinoa.localdomain> (raw)
In-Reply-To: <CAFEAcA8Tt3ygYCZO7ZYkZPwmPQniBu6fLnr+RjNUAmgZdTT0kA@mail.gmail.com>
On Dec 06 16:03, Peter Maydell wrote:
> On Wed, 5 Dec 2018 at 13:44, Aaron Lindsay <aaron@os.amperecomputing.com> wrote:
> >
> > Setup a QEMUTimer to get a callback when we expect counters to next
> > overflow and trigger an interrupt at that time.
> >
> > Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
> > Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
> > ---
> > target/arm/cpu.c | 12 +++++
> > target/arm/cpu.h | 7 +++
> > target/arm/helper.c | 126 +++++++++++++++++++++++++++++++++++++++++---
> > 3 files changed, 139 insertions(+), 6 deletions(-)
> >
> > --- a/target/arm/cpu.h
> > +++ b/target/arm/cpu.h
> > @@ -733,6 +733,8 @@ struct ARMCPU {
> >
> > /* Timers used by the generic (architected) timer */
> > QEMUTimer *gt_timer[NUM_GTIMERS];
> > + /* Timer used by the PMU */
> > + QEMUTimer *pmu_timer;
>
> We don't seem to migrate this timer state. Is that OK? If so,
> a brief comment somewhere with the rationale would be helpful.
cpu_post_load() calls pmccntr_op_finish() and pmevcntr_op_finish() for
each counter via pmu_op_finish(). They handle setting the timer
according to the restored counters' state. I'll add a comment here at
the definition unless you prefer somewhere else.
-Aaron
prev parent reply other threads:[~2018-12-11 14:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-05 13:43 [Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 01/14] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 03/14] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 06/14] target/arm: Implement PMOVSSET Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0 Aaron Lindsay
2018-12-06 15:56 ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-12-05 15:32 ` Aaron Lindsay
2018-12-06 15:59 ` Peter Maydell
2018-12-07 18:00 ` Richard Henderson
2018-12-09 21:58 ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 13/14] target/arm: Implement PMSWINC Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-12-06 16:03 ` Peter Maydell
2018-12-11 14:46 ` Aaron Lindsay [this message]
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