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From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	Wei Huang <wei@redhat.com>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Michael Spradling <mspradli@codeaurora.org>,
	Digant Desai <digantd@codeaurora.org>,
	Aaron Lindsay <aaron@os.amperecomputing.com>
Subject: [Qemu-devel] [PATCH v10 00/14] More fully implement ARM PMUv3
Date: Tue, 11 Dec 2018 15:20:04 +0000	[thread overview]
Message-ID: <20181211151945.29137-1-aaron@os.amperecomputing.com> (raw)

The ARM PMU implementation currently contains a basic cycle counter, but
it is often useful to gather counts of other events, filter them based
on execution mode, and/or be notified on counter overflow. These patches
flesh out the implementations of various PMU registers including
PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent
arbitrary counter types, implement mode filtering, send interrupts on
counter overflow, and add instruction, cycle, and software increment
events.

Since v9 [1] I have made the following changes:
* Added a clarifying comment about how the PMU timer's migration is
  handled
* Added a check against implementing PMCEID[23] if ID_DFR0.PerfMon ==
  0xf
* Added TRACEFILT to the ID_DFR0 field definitions

[1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg00805.html

Aaron Lindsay (14):
  migration: Add post_save function to VMStateDescription
  target/arm: Reorganize PMCCNTR accesses
  target/arm: Swap PMU values before/after migrations
  target/arm: Filter cycle counter based on PMCCFILTR_EL0
  target/arm: Allow AArch32 access for PMCCFILTR
  target/arm: Implement PMOVSSET
  target/arm: Define FIELDs for ID_DFR0
  target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
  target/arm: Add array for supported PMU events, generate
    PMCEID[01]_EL0
  target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
  target/arm: PMU: Add instruction and cycle events
  target/arm: PMU: Set PMCR.N to 4
  target/arm: Implement PMSWINC
  target/arm: Send interrupts on PMU counter overflow

 docs/devel/migration.rst    |   9 +-
 include/migration/vmstate.h |   1 +
 migration/vmstate.c         |  13 +-
 target/arm/cpu.c            |  28 +-
 target/arm/cpu.h            |  81 +++-
 target/arm/cpu64.c          |   4 -
 target/arm/helper.c         | 808 ++++++++++++++++++++++++++++++++----
 target/arm/machine.c        |  24 ++
 8 files changed, 863 insertions(+), 105 deletions(-)

-- 
2.19.2

             reply	other threads:[~2018-12-11 15:20 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-11 15:20 Aaron Lindsay [this message]
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 01/14] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 02/14] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 03/14] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 05/14] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 06/14] target/arm: Implement PMOVSSET Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 07/14] target/arm: Define FIELDs for ID_DFR0 Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2019-02-04 19:22   ` [Qemu-devel] [Qemu-arm] " Laurent Desnogues
2019-02-05 13:41     ` Aaron Lindsay OS
2019-02-05 13:54       ` Laurent Desnogues
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 11/14] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 12/14] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 13/14] target/arm: Implement PMSWINC Aaron Lindsay
2018-12-11 15:20 ` [Qemu-devel] [PATCH v10 14/14] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2019-01-17 20:26   ` Richard Henderson
2019-01-18 21:40     ` Aaron Lindsay
2019-01-18 21:58       ` Richard Henderson
2019-01-11 16:22 ` [Qemu-devel] [PATCH v10 00/14] More fully implement ARM PMUv3 Aaron Lindsay
2019-01-18 14:13 ` Peter Maydell
2019-01-23 20:04   ` Aaron Lindsay OS

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