[Qemu-devel] [PATCH V12 0/5] add pvpanic mmio support

[Qemu-devel] [PATCH V12 0/5] add pvpanic mmio support

[Peng Hao]

The first patches are simple cleanups:
     - patch 1 move the pvpanic device with the 'ocmmon objects' so we compile
               it once for the x86/arm/aarch64 archs,
     - patch 2 simply renames ISA fields/definitions to generic ones.

     Then instead of add/use the MMIO pvpanic device in the virt machine in an
     unique patch, I split it in two distinct patches:
     - patch 3 uses Peng Hao's work, but add the MMIO interface to the existing
        device (no logical change).
     - patch 4 is Peng Hao's work in the virt machine (no logical change).
     - patch 5 add pvpanic device in acpi table in virt machine
     v2 from Peng Hao is:
     https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg03433.html

v3 --> v4
     patch 1,2 no modification.
     patch 3, add TYPE_PANIC_MMIO for distinguishing different bus device,
              virt + isa_pvpanic will abnormally terminate virtual machine.
     patch 4, "pvpanic,mmio" --> "qemu,pvpanic-mmio".
     patch 5, newly added.

v4 --> v5
     patch 1,2 no modification.
     patch 3 delete PvpanicCommonState structure.
     patch 4 VIRT_PVPANIC_MMIO --> VIRT_PVPANIC
             correct VIRT_PVPANIC's overlap start address
     patch 5 no modification.

v5 --> v6
     add document.

v6 --> v7
     patch 5 modify device name from "PANC" to "PEVT".
     patch 6 modify document description.

v7 --> v8
     add configure interface for pvpanic-mmio

v8 --> v9
     revert "moving structure definition to header file"
     because of compile error in x86.

v9 --> v10
     Modify document.
     Repair missing header files.

v10 --> v11
     change configure interface in virt machine configure parameters.

v11 --> v12
     realize pvpanic as a pci device and use the mmio of pci device.

Philippe Mathieu-Daudé (2):
  hw/misc/pvpanic: Build the pvpanic device in $(common-obj)
  hw/misc/pvpanic: Cosmetic renaming

Peng Hao (3):
  pvpanic : update pvpanic document
  hw/arm/virt: Use the pvpanic device
  pvpanic: add mmio interface as a pci device

default-configs/arm-softmmu.mak |  1 +
docs/specs/pvpanic.txt          | 13 +++++-
hw/misc/Makefile.objs           |  2 +-
hw/misc/pvpanic.c               | 91 +++++++++++++++++++++++++++++++++--------
include/hw/misc/pvpanic.h       |  1 +
include/hw/pci/pci.h            |  1 +
6 files changed, 91 insertions(+), 18 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH V12 1/5] hw/misc/pvpanic: Build the pvpanic device in $(common-obj)

[Peng Hao]

From: Philippe Mathieu-Daudé <philmd@redhat.com>

The 'pvpanic' ISA device can be use by any machine with an ISA bus.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
---
 hw/misc/Makefile.objs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 680350b..c387ce4 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
 common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
 common-obj-$(CONFIG_EDU) += edu.o
 common-obj-$(CONFIG_PCA9552) += pca9552.o
+common-obj-$(CONFIG_PVPANIC) += pvpanic.o
 
 common-obj-y += unimp.o
 common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o
@@ -70,7 +71,6 @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
 obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
 obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
 
-obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_AUX) += auxbus.o
 obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
 obj-$(CONFIG_MSF2) += msf2-sysreg.o
-- 
1.8.3.1

[Qemu-devel] [PATCH V12 2/5] hw/misc/pvpanic: Cosmetic renaming

[Peng Hao]

From: Philippe Mathieu-Daudé <philmd@redhat.com>

To ease the MMIO device addition in the next patch, rename:
- ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE.
- MemoryRegion io -> mr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
---
 hw/misc/pvpanic.c | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index 9d8961b..0f23a67 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -25,8 +25,8 @@
 /* The pv event value */
 #define PVPANIC_PANICKED        (1 << PVPANIC_F_PANICKED)
 
-#define ISA_PVPANIC_DEVICE(obj)    \
-    OBJECT_CHECK(PVPanicState, (obj), TYPE_PVPANIC)
+#define PVPANIC_ISA_DEVICE(obj)    \
+    OBJECT_CHECK(PVPanicISAState, (obj), TYPE_PVPANIC)
 
 static void handle_event(int event)
 {
@@ -45,12 +45,16 @@ static void handle_event(int event)
 
 #include "hw/isa/isa.h"
 
-typedef struct PVPanicState {
+/* PVPanicISAState for ISA device and
+ * use ioport.
+ */
+typedef struct PVPanicISAState {
     ISADevice parent_obj;
-
-    MemoryRegion io;
+    /*< private>*/
     uint16_t ioport;
-} PVPanicState;
+    /*<public>*/
+    MemoryRegion mr;
+} PVPanicISAState;
 
 /* return supported events on read */
 static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned size)
@@ -75,15 +79,15 @@ static const MemoryRegionOps pvpanic_ops = {
 
 static void pvpanic_isa_initfn(Object *obj)
 {
-    PVPanicState *s = ISA_PVPANIC_DEVICE(obj);
+    PVPanicISAState *s = PVPANIC_ISA_DEVICE(obj);
 
-    memory_region_init_io(&s->io, OBJECT(s), &pvpanic_ops, s, "pvpanic", 1);
+    memory_region_init_io(&s->mr, OBJECT(s), &pvpanic_ops, s, "pvpanic", 1);
 }
 
 static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
 {
     ISADevice *d = ISA_DEVICE(dev);
-    PVPanicState *s = ISA_PVPANIC_DEVICE(dev);
+    PVPanicISAState *s = PVPANIC_ISA_DEVICE(dev);
     FWCfgState *fw_cfg = fw_cfg_find();
     uint16_t *pvpanic_port;
 
@@ -96,11 +100,11 @@ static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
     fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
                     sizeof(*pvpanic_port));
 
-    isa_register_ioport(d, &s->io, s->ioport);
+    isa_register_ioport(d, &s->mr, s->ioport);
 }
 
 static Property pvpanic_isa_properties[] = {
-    DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
+    DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -116,7 +120,7 @@ static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
 static TypeInfo pvpanic_isa_info = {
     .name          = TYPE_PVPANIC,
     .parent        = TYPE_ISA_DEVICE,
-    .instance_size = sizeof(PVPanicState),
+    .instance_size = sizeof(PVPanicISAState),
     .instance_init = pvpanic_isa_initfn,
     .class_init    = pvpanic_isa_class_init,
 };
-- 
1.8.3.1

[Qemu-devel] [PATCH V12 3/5] hw/misc/pvpanic: Add the PCI interface

[Peng Hao]

Add pvpanic new type "TYPE_PVPANIC_PCI"

Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
---
 hw/misc/pvpanic.c         | 62 ++++++++++++++++++++++++++++++++++++++++++++---
 include/hw/misc/pvpanic.h |  1 +
 include/hw/pci/pci.h      |  1 +
 3 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index 0f23a67..9fb9168 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -2,10 +2,12 @@
  * QEMU simulated pvpanic device.
  *
  * Copyright Fujitsu, Corp. 2013
+ * Copyright (c) 2018 ZTE Ltd.
  *
  * Authors:
  *     Wen Congyang <wency@cn.fujitsu.com>
  *     Hu Tao <hutao@cn.fujitsu.com>
+ *     Peng Hao <peng.hao2@zte.com.cn>
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -18,6 +20,7 @@
 
 #include "hw/nvram/fw_cfg.h"
 #include "hw/misc/pvpanic.h"
+#include "hw/pci/pci.h"
 
 /* The bit of supported pv event */
 #define PVPANIC_F_PANICKED      0
@@ -27,6 +30,8 @@
 
 #define PVPANIC_ISA_DEVICE(obj)    \
     OBJECT_CHECK(PVPanicISAState, (obj), TYPE_PVPANIC)
+#define PVPANIC_PCI_DEVICE(obj)    \
+    OBJECT_CHECK(PVPanicPCIState, (obj), TYPE_PVPANIC_PCI)
 
 static void handle_event(int event)
 {
@@ -56,21 +61,31 @@ typedef struct PVPanicISAState {
     MemoryRegion mr;
 } PVPanicISAState;
 
+/* PVPanicPCIState for PCI device and
+ * use mmio.
+ */
+typedef struct PVPanicPCIState {
+    /*< private>*/
+    PCIDevice dev;
+
+    /*<public>*/
+    MemoryRegion mr;
+} PVPanicPCIState;
 /* return supported events on read */
-static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned size)
+static uint64_t pvpanic_read(void *opaque, hwaddr addr, unsigned size)
 {
     return PVPANIC_PANICKED;
 }
 
-static void pvpanic_ioport_write(void *opaque, hwaddr addr, uint64_t val,
+static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
                                  unsigned size)
 {
     handle_event(val);
 }
 
 static const MemoryRegionOps pvpanic_ops = {
-    .read = pvpanic_ioport_read,
-    .write = pvpanic_ioport_write,
+    .read = pvpanic_read,
+    .write = pvpanic_write,
     .impl = {
         .min_access_size = 1,
         .max_access_size = 1,
@@ -125,9 +140,48 @@ static TypeInfo pvpanic_isa_info = {
     .class_init    = pvpanic_isa_class_init,
 };
 
+/* pvpanic pci device*/
+
+static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp)
+{
+    PVPanicPCIState *s = DO_UPCAST(PVPanicPCIState, dev, dev);
+
+    memory_region_init_io(&s->mr, OBJECT(s), &pvpanic_ops, s,
+                          TYPE_PVPANIC_PCI, 2);
+    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mr);
+}
+
+static void pvpanic_pci_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
+
+    pc->realize = pvpanic_pci_realizefn;
+    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
+    pc->device_id = PCI_DEVICE_ID_REDHAT_PVPANIC;
+    pc->revision = 1;
+    pc->class_id = PCI_CLASS_SYSTEM_OTHER;
+
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static TypeInfo pvpanic_pci_info = {
+    .name          = TYPE_PVPANIC_PCI,
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PVPanicPCIState),
+    .class_init    = pvpanic_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+        { }
+    }
+};
+
+
 static void pvpanic_register_types(void)
 {
     type_register_static(&pvpanic_isa_info);
+    type_register_static(&pvpanic_pci_info);
 }
 
 type_init(pvpanic_register_types)
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
index 1ee071a..477cc36 100644
--- a/include/hw/misc/pvpanic.h
+++ b/include/hw/misc/pvpanic.h
@@ -15,6 +15,7 @@
 #define HW_MISC_PVPANIC_H
 
 #define TYPE_PVPANIC "pvpanic"
+#define TYPE_PVPANIC_PCI "pvpanic-pci"
 
 #define PVPANIC_IOPORT_PROP "ioport"
 
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index e6514bb..92622f7 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -103,6 +103,7 @@ extern bool pci_available;
 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
+#define PCI_DEVICE_ID_REDHAT_PVPANIC     0x0101
 
 #define FMT_PCIBUS                      PRIx64
 
-- 
1.8.3.1

[Qemu-devel] [PATCH V12 4/5] hw/arm/virt: Use the pvpanic pci device

[Peng Hao]

Add pvpanic device in arm virt machine config file.

Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
---
 default-configs/arm-softmmu.mak | 1 +
 1 file changed, 1 insertion(+)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 2420491..50345df 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -159,3 +159,4 @@ CONFIG_PCI_DESIGNWARE=y
 CONFIG_STRONGARM=y
 CONFIG_HIGHBANK=y
 CONFIG_MUSICPAL=y
+CONFIG_PVPANIC=y
-- 
1.8.3.1

[Qemu-devel] [PATCH] pvpanic : update pvpanic document

[Peng Hao]

Add mmio mode as a pci device support info in docs/specs/pvpanic.txt.

Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
---
 docs/specs/pvpanic.txt | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
index c7bbacc..6d62d72 100644
--- a/docs/specs/pvpanic.txt
+++ b/docs/specs/pvpanic.txt
@@ -1,7 +1,7 @@
 PVPANIC DEVICE
 ==============
 
-pvpanic device is a simulated ISA device, through which a guest panic
+pvpanic device is a simulated device, through which a guest panic
 event is sent to qemu, and a QMP event is generated. This allows
 management apps (e.g. libvirt) to be notified and respond to the event.
 
@@ -9,6 +9,10 @@ The management app has the option of waiting for GUEST_PANICKED events,
 and/or polling for guest-panicked RunState, to learn when the pvpanic
 device has fired a panic event.
 
+The pvpanic device can be implemented as an ISA device (using IOPORT),
+or, since qemu 4.0, as a PCI device (using MMIO address space of pci
+device).
+
 ISA Interface
 -------------
 
@@ -19,6 +23,13 @@ Software should set only bits both itself and the device recognize.
 Currently, only bit 0 is recognized, setting it indicates a guest panic
 has happened.
 
+PCI Interface
+-------------
+
+The PCI interface is similar to the ISA interface except that it uses
+MMIO. For example, the arm virt machine could enable pvpanic-pci device 
+according to adding "-device pvpanic-pci" in qemu command.
+
 ACPI Interface
 --------------
 
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH V12 0/5] add pvpanic mmio support

[peng.hao2]

>v10 --> v11
>change configure interface in virt machine configure parameters.
>
>v11 --> v12
>realize pvpanic as a pci device and use the mmio of pci device.
>
>Philippe Mathieu-Daudé (2):
>hw/misc/pvpanic: Build the pvpanic device in $(common-obj)
>hw/misc/pvpanic: Cosmetic renaming
>
>Peng Hao (3):
>pvpanic : update pvpanic document
>hw/arm/virt: Use the pvpanic device
>pvpanic: add mmio interface as a pci device
Hi , I resubmit a series patches for realizeing pvpanic as a pci device.
and I want to confirm if these patches meet the requirements. 
I know there are still some imperfections in this series of patches, 
such as how to avoid x86/pvpanic using ISA/pvpanic and PCI/pvpanic at the same time.
 But I want to confirm if there is a problem with the overall direction of implementation 
as a PCI device.Then I can resubmit patches to kernel for replacing the previous ones.

Thanks.

Re: [Qemu-devel] [PATCH] pvpanic : update pvpanic document

[Andrew Jones]

On Thu, Dec 06, 2018 at 07:26:00PM +0800, Peng Hao wrote:
> Add mmio mode as a pci device support info in docs/specs/pvpanic.txt.
> 
> Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
> ---
>  docs/specs/pvpanic.txt | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
> index c7bbacc..6d62d72 100644
> --- a/docs/specs/pvpanic.txt
> +++ b/docs/specs/pvpanic.txt
> @@ -1,7 +1,7 @@
>  PVPANIC DEVICE
>  ==============
>  
> -pvpanic device is a simulated ISA device, through which a guest panic
> +pvpanic device is a simulated device, through which a guest panic
>  event is sent to qemu, and a QMP event is generated. This allows
>  management apps (e.g. libvirt) to be notified and respond to the event.
>  
> @@ -9,6 +9,10 @@ The management app has the option of waiting for GUEST_PANICKED events,
>  and/or polling for guest-panicked RunState, to learn when the pvpanic
>  device has fired a panic event.
>  
> +The pvpanic device can be implemented as an ISA device (using IOPORT),
> +or, since qemu 4.0, as a PCI device (using MMIO address space of pci
> +device).

I'd drop the part in (). Just end with 'as a PCI device.' The MMIO stuff
is described below in the "PCI Interface" section.

> +
>  ISA Interface
>  -------------
>  
> @@ -19,6 +23,13 @@ Software should set only bits both itself and the device recognize.
>  Currently, only bit 0 is recognized, setting it indicates a guest panic
>  has happened.
>  
> +PCI Interface
> +-------------
> +
> +The PCI interface is similar to the ISA interface except that it uses
> +MMIO.

uses an MMIO address space provided by its BAR0.

Should describe that the MMIO address is two bytes in size here as well.


> For example, the arm virt machine could enable pvpanic-pci device 
> +according to adding "-device pvpanic-pci" in qemu command.

For example, the arm virt machine may enable a pvpanic device by
adding '-device pvpanic-pci' to the command line.

> +
>  ACPI Interface
>  --------------
>  
> -- 
> 1.8.3.1
> 
>

Thanks,
drew 

Re: [Qemu-devel] [PATCH V12 0/5] add pvpanic mmio support

[Andrew Jones]

On Thu, Dec 06, 2018 at 07:25:55PM +0800, Peng Hao wrote:
> The first patches are simple cleanups:
>      - patch 1 move the pvpanic device with the 'ocmmon objects' so we compile
>                it once for the x86/arm/aarch64 archs,
>      - patch 2 simply renames ISA fields/definitions to generic ones.
> 
>      Then instead of add/use the MMIO pvpanic device in the virt machine in an
>      unique patch, I split it in two distinct patches:
>      - patch 3 uses Peng Hao's work, but add the MMIO interface to the existing
>         device (no logical change).
>      - patch 4 is Peng Hao's work in the virt machine (no logical change).
>      - patch 5 add pvpanic device in acpi table in virt machine
>      v2 from Peng Hao is:
>      https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg03433.html
> 
> v3 --> v4
>      patch 1,2 no modification.
>      patch 3, add TYPE_PANIC_MMIO for distinguishing different bus device,
>               virt + isa_pvpanic will abnormally terminate virtual machine.
>      patch 4, "pvpanic,mmio" --> "qemu,pvpanic-mmio".
>      patch 5, newly added.
> 
> v4 --> v5
>      patch 1,2 no modification.
>      patch 3 delete PvpanicCommonState structure.
>      patch 4 VIRT_PVPANIC_MMIO --> VIRT_PVPANIC
>              correct VIRT_PVPANIC's overlap start address
>      patch 5 no modification.
> 
> v5 --> v6
>      add document.
> 
> v6 --> v7
>      patch 5 modify device name from "PANC" to "PEVT".
>      patch 6 modify document description.
> 
> v7 --> v8
>      add configure interface for pvpanic-mmio
> 
> v8 --> v9
>      revert "moving structure definition to header file"
>      because of compile error in x86.
> 
> v9 --> v10
>      Modify document.
>      Repair missing header files.
> 
> v10 --> v11
>      change configure interface in virt machine configure parameters.
> 
> v11 --> v12
>      realize pvpanic as a pci device and use the mmio of pci device.

Do you have a pointer to the kernel patches?

Thanks,
drew


> 
> Philippe Mathieu-Daudé (2):
>   hw/misc/pvpanic: Build the pvpanic device in $(common-obj)
>   hw/misc/pvpanic: Cosmetic renaming
> 
> Peng Hao (3):
>   pvpanic : update pvpanic document
>   hw/arm/virt: Use the pvpanic device
>   pvpanic: add mmio interface as a pci device
> 
> default-configs/arm-softmmu.mak |  1 +
> docs/specs/pvpanic.txt          | 13 +++++-
> hw/misc/Makefile.objs           |  2 +-
> hw/misc/pvpanic.c               | 91 +++++++++++++++++++++++++++++++++--------
> include/hw/misc/pvpanic.h       |  1 +
> include/hw/pci/pci.h            |  1 +
> 6 files changed, 91 insertions(+), 18 deletions(-)
> 
> -- 
> 1.8.3.1
> 
> 

Re: [Qemu-devel] [PATCH V12 0/5] add pvpanic mmio support

[peng.hao2]

>> v11 --> v12
>>      realize pvpanic as a pci device and use the mmio of pci device.
>
>Do you have a pointer to the kernel patches?
>
>Thanks,
>>drew
>
I'm still sorting out the code for the kernel part, and I haven't submitted a patch yet.

Re: [Qemu-devel] [PATCH V12 0/5] add pvpanic mmio support

[Auger Eric]

Hi Peng,

On 12/12/18 2:54 AM, peng.hao2@zte.com.cn wrote:
>>> v11 --> v12
>>>      realize pvpanic as a pci device and use the mmio of pci device.
>>
>> Do you have a pointer to the kernel patches?
>>
>> Thanks,
>>> drew
>>
> I'm still sorting out the code for the kernel part, and I haven't submitted a patch yet.
> 

What is the status of the effort to get this PCI PVPANIC device available?

I am unsure about the kernel driver status. I found

[PATCH V6 0/4] add pvpanic driver framework
https://lwn.net/Articles/780193/

Thank you in advance

Best Regards

Eric