From: David Gibson <david@gibson.dropbear.id.au>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: gkurz@kaod.org, "Cédric Le Goater" <clg@kaod.org>,
"Laurent Vivier" <lvivier@redhat.com>,
spopovyc@redhat.com, qemu-ppc <qemu-ppc@nongnu.org>,
"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213
Date: Sat, 15 Dec 2018 20:09:00 +1100 [thread overview]
Message-ID: <20181215090900.GQ29278@umbus.fritz.box> (raw)
In-Reply-To: <CAFEAcA_4xV2M0Tgw6KSSQ7DOhv3r=FhETH_Yhmg2h0UT3AYS9g@mail.gmail.com>
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On Fri, Dec 14, 2018 at 04:03:08PM +0000, Peter Maydell wrote:
> On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
> >
> > The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
> >
> > Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
> >
> > are available in the Git repository at:
> >
> > git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
> >
> > for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
> >
> > spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
> >
> > ----------------------------------------------------------------
> > ppc patch queue 2018-12-13
> >
> > Here's the first ppc and spapr pull request for 4.0. Highlights are:
> >
> > * The start of support for the POWER9 "XIVE" interrupt controller
> > (not complete enough to use yet, but we're getting there)
> > * A number of g_new vs. g_malloc cleanups
> > * Some IRQ wiring cleanups
> > * A fix for how we advertise NUMA nodes to the guest for pseries
> >
> > ---------------------------------------------------------------
>
>
> Compile errors in the windows cross-build. These look like
> they're assumptions that "long" is 64 bits, which it is not on Windows.
> For instance the PPC_BIT macro should be using the ULL suffix, not UL
> ("UL" is almost always a bug: either the constant is 32-bit, in
> which case "U" is what you want, or it's 64-bit and you need "ULL").
Bother, sorry. I got sidetracked debugging some problems that turned
out to be in master and forgot to run the windows builds.
> Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
> a bit dubious -- this should be rephrased to use ctz32() or ctz64()
> instead.
>
> In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
> #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
> # define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> expansion of macro 'GETFIELD_BE64'
> GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
> #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
> expansion of macro 'EAS_END_BLOCK'
> GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
> #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> expansion of macro 'GETFIELD_BE64'
> GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
> #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
> # define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> expansion of macro 'GETFIELD_BE64'
> GETFIELD_BE64(EAS_END_INDEX, eas.w),
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> note: in expansion of macro 'PPC_BITMASK'
> #define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
> expansion of macro 'EAS_END_INDEX'
> GETFIELD_BE64(EAS_END_INDEX, eas.w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
> #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> expansion of macro 'GETFIELD_BE64'
> GETFIELD_BE64(EAS_END_INDEX, eas.w),
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
> 'xive_eas_pic_print_info':
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
> #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
> # define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
> (uint8_t) GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
> #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> expansion of macro 'EAS_END_BLOCK'
> (uint8_t) GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
> #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
> (uint8_t) GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
> #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> expansion of macro 'EAS_END_BLOCK'
> (uint8_t) GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
> #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
> (uint8_t) GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
> #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
> # define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> expansion of macro 'GETFIELD_BE64'
> (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> note: in expansion of macro 'PPC_BITMASK'
> #define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
> expansion of macro 'EAS_END_INDEX'
> (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
> #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
> #define GETFIELD_BE64(m, v) GETFIELD(m, be64_to_cpu(v))
> ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> expansion of macro 'GETFIELD_BE64'
> (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> ^
>
>
> thanks
> -- PMM
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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prev parent reply other threads:[~2018-12-16 6:18 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 4:00 [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213 David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 01/27] spapr: Fix ibm, max-associativity-domains property number of nodes David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 02/27] target/ppc: tcg: Implement addex instruction David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 03/27] spapr: drop redundant statement in spapr_populate_drconf_memory() David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 04/27] target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n) David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 05/27] spapr: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 06/27] ppc405_boards: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 07/27] ppc405_uc: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 08/27] ppc440_bamboo: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 09/27] sam460ex: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 10/27] virtex_ml507: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 11/27] mac_newworld: simplify IRQ wiring David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 12/27] e500: " David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 13/27] ppc/xive: introduce a XIVE interrupt source model David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 14/27] ppc/xive: add support for the LSI interrupt sources David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 15/27] ppc/xive: introduce the XiveNotifier interface David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 16/27] ppc/xive: introduce the XiveRouter model David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 17/27] ppc/xive: introduce the XIVE Event Notification Descriptors David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 18/27] spapr: initialize VSMT before initializing the IRQ backend David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 19/27] spapr: introduce a spapr_irq_init() routine David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 20/27] spapr: export and rename the xics_max_server_number() routine David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 21/27] Changes requirement for "vsubsbs" instruction David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 22/27] ppc/xive: add support for the END Event State Buffers David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 23/27] ppc/xive: introduce the XIVE interrupt thread context David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 24/27] ppc/xive: introduce a simplified XIVE presenter David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 25/27] ppc/xive: notify the CPU when the interrupt priority is more privileged David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 26/27] spapr/xive: introduce a XIVE interrupt controller David Gibson
2018-12-13 4:01 ` [Qemu-devel] [PULL 27/27] spapr/xive: use the VCPU id as a NVT identifier David Gibson
2018-12-13 7:43 ` [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213 no-reply
2018-12-13 12:08 ` David Gibson
2018-12-13 12:57 ` Cédric Le Goater
2018-12-14 16:03 ` Peter Maydell
2018-12-14 17:49 ` Cédric Le Goater
2018-12-17 1:03 ` David Gibson
2018-12-17 7:41 ` [Qemu-devel] [Qemu-ppc] " Howard Spoelstra
2018-12-17 8:04 ` [Qemu-devel] " Cédric Le Goater
2018-12-17 10:11 ` Cédric Le Goater
2018-12-15 9:09 ` David Gibson [this message]
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