From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41195) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ4On-0001s8-1H for qemu-devel@nongnu.org; Mon, 17 Dec 2018 20:42:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ4Cg-0008Bv-5o for qemu-devel@nongnu.org; Mon, 17 Dec 2018 20:29:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:34728) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZ4Cf-0008Bb-W5 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 20:29:46 -0500 Date: Mon, 17 Dec 2018 20:29:37 -0500 From: "Michael S. Tsirkin" Message-ID: <20181217202850-mutt-send-email-mst@kernel.org> References: <154464279386.9828.10219496338109023342.stgit@gimli.home> <154464358344.9828.234735873419417928.stgit@gimli.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <154464358344.9828.234735873419417928.stgit@gimli.home> Subject: Re: [Qemu-devel] [PATCH v5 6/8] pcie: Allow generic PCIe root port to specify link speed and width List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex Williamson Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , Geoffrey McRae , Eric Auger On Wed, Dec 12, 2018 at 12:39:43PM -0700, Alex Williamson wrote: > Allow users to experimentally specify speed and width values for the > generic PCIe root port. Defaults remain at 2.5GT/s & x1 for > compatiblity with the intent to only support changing defaults via > machine types for now. > > Note for libvirt testing that pcie-root-port controllers are given > default names like "pci.7" which don't play well with using the > "-set device.$name.$prop=$value" options accessible to us via > options. The solution is to add an to the > pcie-root-port , for example: > > > > > >
> > > The "ua-" here is a mandatory prefix. We can then use: > > > > > > > > > or, without an alias, set globals such as: > > > > > > > > > Cc: Michael S. Tsirkin > Cc: Marcel Apfelbaum > Tested-by: Geoffrey McRae > Reviewed-by: Eric Auger > Signed-off-by: Alex Williamson > --- > hw/pci-bridge/gen_pcie_root_port.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c > index 299de429ec1e..ca5418a89dd2 100644 > --- a/hw/pci-bridge/gen_pcie_root_port.c > +++ b/hw/pci-bridge/gen_pcie_root_port.c > @@ -124,6 +124,10 @@ static Property gen_rp_props[] = { > res_reserve.mem_pref_32, -1), > DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, > res_reserve.mem_pref_64, -1), > + DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, > + speed, PCIE_LINK_SPEED_2_5), > + DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, > + width, PCIE_LINK_WIDTH_1), > DEFINE_PROP_END_OF_LIST() > }; > Doesn't seem to build. Just where is DEFINE_PROP_PCIE_LINK_SPEED defined? -- MST