From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ934-0001sC-JD for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92v-0002xE-0O for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:10 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:45014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92u-0001t1-Ni for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:00 -0500 Received: by mail-pf1-x444.google.com with SMTP id u6so7640804pfh.11 for ; Mon, 17 Dec 2018 22:39:16 -0800 (PST) From: Richard Henderson Date: Mon, 17 Dec 2018 22:38:38 -0800 Message-Id: <20181218063911.2112-2-richard.henderson@linaro.org> In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 01/34] tcg: Add logical simplifications during gvec expand List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au We handle many of these during integer expansion, and the rest of them during integer optimization. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 61c25f5784..ec231b78fb 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1840,7 +1840,12 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, .opc = INDEX_op_and_vec, .prefer_i64 = TCG_TARGET_REG_BITS == 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs == bofs) { + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1853,7 +1858,12 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, .opc = INDEX_op_or_vec, .prefer_i64 = TCG_TARGET_REG_BITS == 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs == bofs) { + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1866,7 +1876,12 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, .opc = INDEX_op_xor_vec, .prefer_i64 = TCG_TARGET_REG_BITS == 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs == bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1879,7 +1894,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, .opc = INDEX_op_andc_vec, .prefer_i64 = TCG_TARGET_REG_BITS == 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs == bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1892,7 +1912,12 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, .opc = INDEX_op_orc_vec, .prefer_i64 = TCG_TARGET_REG_BITS == 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs == bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } static const GVecGen2s gop_ands = { -- 2.17.2