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From: David Gibson <david@gibson.dropbear.id.au>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, mark.cave-ayland@ilande.co.uk,
	qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations
Date: Wed, 19 Dec 2018 17:31:13 +1100	[thread overview]
Message-ID: <20181219063113.GO30570@umbus.fritz.box> (raw)
In-Reply-To: <20181218063911.2112-20-richard.henderson@linaro.org>

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On Mon, Dec 17, 2018 at 10:38:56PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target/ppc/helper.h                 |  3 ---
>  target/ppc/int_helper.c             | 15 ------------
>  target/ppc/translate/vmx-impl.inc.c | 36 +++++++----------------------
>  3 files changed, 8 insertions(+), 46 deletions(-)
> 
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 553ff500c8..2aa60e5d36 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -246,9 +246,6 @@ DEF_HELPER_3(vrld, void, avr, avr, avr)
>  DEF_HELPER_3(vsl, void, avr, avr, avr)
>  DEF_HELPER_3(vsr, void, avr, avr, avr)
>  DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
> -DEF_HELPER_2(vspltisb, void, avr, i32)
> -DEF_HELPER_2(vspltish, void, avr, i32)
> -DEF_HELPER_2(vspltisw, void, avr, i32)
>  DEF_HELPER_3(vspltb, void, avr, avr, i32)
>  DEF_HELPER_3(vsplth, void, avr, avr, i32)
>  DEF_HELPER_3(vspltw, void, avr, avr, i32)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 4547453ef1..e44c0d90ee 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -2066,21 +2066,6 @@ VNEG(vnegw, s32)
>  VNEG(vnegd, s64)
>  #undef VNEG
>  
> -#define VSPLTI(suffix, element, splat_type)                     \
> -    void helper_vspltis##suffix(ppc_avr_t *r, uint32_t splat)   \
> -    {                                                           \
> -        splat_type x = (int8_t)(splat << 3) >> 3;               \
> -        int i;                                                  \
> -                                                                \
> -        for (i = 0; i < ARRAY_SIZE(r->element); i++) {          \
> -            r->element[i] = x;                                  \
> -        }                                                       \
> -    }
> -VSPLTI(b, s8, int8_t)
> -VSPLTI(h, s16, int16_t)
> -VSPLTI(w, s32, int32_t)
> -#undef VSPLTI
> -
>  #define VSR(suffix, element, mask)                                      \
>      void helper_vsr##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)   \
>      {                                                                   \
> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
> index e353d3f174..be638cdb1a 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -720,25 +720,21 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
>  GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
>                   vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
>  
> -#define GEN_VXFORM_SIMM(name, opc2, opc3)                               \
> +#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3)                       \
>  static void glue(gen_, name)(DisasContext *ctx)                         \
>      {                                                                   \
> -        TCGv_ptr rd;                                                    \
> -        TCGv_i32 simm;                                                  \
> +        int simm;                                                       \
>          if (unlikely(!ctx->altivec_enabled)) {                          \
>              gen_exception(ctx, POWERPC_EXCP_VPU);                       \
>              return;                                                     \
>          }                                                               \
> -        simm = tcg_const_i32(SIMM5(ctx->opcode));                       \
> -        rd = gen_avr_ptr(rD(ctx->opcode));                              \
> -        gen_helper_##name (rd, simm);                                   \
> -        tcg_temp_free_i32(simm);                                        \
> -        tcg_temp_free_ptr(rd);                                          \
> +        simm = SIMM5(ctx->opcode);                                      \
> +        tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm);      \
>      }
>  
> -GEN_VXFORM_SIMM(vspltisb, 6, 12);
> -GEN_VXFORM_SIMM(vspltish, 6, 13);
> -GEN_VXFORM_SIMM(vspltisw, 6, 14);
> +GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
> +GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
> +GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
>  
>  #define GEN_VXFORM_NOA(name, opc2, opc3)                                \
>  static void glue(gen_, name)(DisasContext *ctx)                                 \
> @@ -818,22 +814,6 @@ GEN_VXFORM_NOA(vprtybw, 1, 24);
>  GEN_VXFORM_NOA(vprtybd, 1, 24);
>  GEN_VXFORM_NOA(vprtybq, 1, 24);
>  
> -#define GEN_VXFORM_SIMM(name, opc2, opc3)                               \
> -static void glue(gen_, name)(DisasContext *ctx)                                 \
> -    {                                                                   \
> -        TCGv_ptr rd;                                                    \
> -        TCGv_i32 simm;                                                  \
> -        if (unlikely(!ctx->altivec_enabled)) {                          \
> -            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
> -            return;                                                     \
> -        }                                                               \
> -        simm = tcg_const_i32(SIMM5(ctx->opcode));                       \
> -        rd = gen_avr_ptr(rD(ctx->opcode));                              \
> -        gen_helper_##name (rd, simm);                                   \
> -        tcg_temp_free_i32(simm);                                        \
> -        tcg_temp_free_ptr(rd);                                          \
> -    }
> -
>  #define GEN_VXFORM_UIMM(name, opc2, opc3)                               \
>  static void glue(gen_, name)(DisasContext *ctx)                                 \
>      {                                                                   \
> @@ -1255,7 +1235,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
>  #undef GEN_VXRFORM_DUAL
>  #undef GEN_VXRFORM1
>  #undef GEN_VXRFORM
> -#undef GEN_VXFORM_SIMM
> +#undef GEN_VXFORM_DUPI
>  #undef GEN_VXFORM_NOA
>  #undef GEN_VXFORM_UIMM
>  #undef GEN_VAFORM_PAIRED

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2018-12-19  7:49 UTC|newest]

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-18  6:38 [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 01/34] tcg: Add logical simplifications during gvec expand Richard Henderson
2018-12-19  5:36   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or Richard Henderson
2018-12-19  5:37   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 03/34] tcg: Add gvec expanders for nand, nor, eqv Richard Henderson
2018-12-19  5:39   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 04/34] tcg: Add write_aofs to GVecGen4 Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 05/34] tcg: Add opcodes for vector saturated arithmetic Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 06/34] tcg/i386: Implement vector saturating arithmetic Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 07/34] tcg: Add opcodes for vector minmax arithmetic Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 08/34] tcg/i386: Implement " Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 09/34] target/arm: Use vector minmax expanders for aarch64 Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 10/34] target/arm: Use vector minmax expanders for aarch32 Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 11/34] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access Richard Henderson
2018-12-19  6:15   ` David Gibson
2018-12-19 12:29     ` Mark Cave-Ayland
2018-12-20 16:52       ` Mark Cave-Ayland
2018-12-18  6:38 ` [Qemu-devel] [PATCH 12/34] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX " Richard Henderson
2018-12-19  6:15   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 13/34] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR " Richard Henderson
2018-12-19  6:17   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env Richard Henderson
2018-12-19  6:20   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 15/34] target/ppc: merge ppc_vsr_t and ppc_avr_t union types Richard Henderson
2018-12-19  6:21   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 16/34] target/ppc: move FP and VMX registers into aligned vsr register array Richard Henderson
2018-12-19  6:27   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations Richard Henderson
2018-12-19  6:29   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 18/34] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over " Richard Henderson
2018-12-19  6:29   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] " Richard Henderson
2018-12-19  6:31   ` David Gibson [this message]
2018-12-18  6:38 ` [Qemu-devel] [PATCH 20/34] target/ppc: convert vsplt[bhw] " Richard Henderson
2018-12-19  6:32   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic " Richard Henderson
2018-12-19  6:32   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 22/34] target/ppc: convert VSX logical operations to " Richard Henderson
2018-12-19  6:33   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 23/34] target/ppc: convert xxspltib " Richard Henderson
2018-12-19  6:34   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw " Richard Henderson
2018-12-19  6:35   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel " Richard Henderson
2018-12-19  6:35   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 26/34] target/ppc: Pass integer to helper_mtvscr Richard Henderson
2018-12-19  6:37   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb Richard Henderson
2018-12-19  6:38   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 28/34] target/ppc: Remove vscr_nj and vscr_sat Richard Henderson
2018-12-19  6:38   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr Richard Henderson
2018-12-19  6:39   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 30/34] target/ppc: Use mtvscr/mfvscr for vmstate Richard Henderson
2018-12-19  6:40   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 31/34] target/ppc: Add set_vscr_sat Richard Henderson
2018-12-19  6:40   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field Richard Henderson
2018-12-19  6:41   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations Richard Henderson
2018-12-19  6:42   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 34/34] target/ppc: convert vmin* and vmax* " Richard Henderson
2018-12-19  6:42   ` David Gibson
2018-12-18  9:49 ` [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements Mark Cave-Ayland
2018-12-18 14:51   ` Mark Cave-Ayland
2018-12-18 15:07     ` Richard Henderson
2018-12-18 15:22       ` Mark Cave-Ayland
2018-12-18 15:05   ` Mark Cave-Ayland
2018-12-18 15:17     ` Richard Henderson
2018-12-18 15:26       ` Mark Cave-Ayland
2018-12-18 16:16         ` Richard Henderson
2019-01-03 14:58   ` Mark Cave-Ayland
2019-01-03 18:31 ` Mark Cave-Ayland
2019-01-04 22:33   ` Richard Henderson

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