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From: David Gibson <david@gibson.dropbear.id.au>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, mark.cave-ayland@ilande.co.uk,
	qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 22/34] target/ppc: convert VSX logical operations to vector operations
Date: Wed, 19 Dec 2018 17:33:39 +1100	[thread overview]
Message-ID: <20181219063338.GR30570@umbus.fritz.box> (raw)
In-Reply-To: <20181218063911.2112-23-richard.henderson@linaro.org>

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On Mon, Dec 17, 2018 at 10:38:59PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target/ppc/translate/vsx-impl.inc.c | 43 ++++++++++++-----------------
>  1 file changed, 17 insertions(+), 26 deletions(-)
> 
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 1608ad48b1..8ab1290026 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -10,6 +10,11 @@ static inline void set_vsr(int n, TCGv_i64 src)
>      tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1]));
>  }
>  
> +static inline int vsr_full_offset(int n)
> +{
> +    return offsetof(CPUPPCState, vsr[n].u64[0]);
> +}
> +
>  static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
>  {
>      if (n < 32) {
> @@ -1214,40 +1219,26 @@ static void gen_xxbrw(DisasContext *ctx)
>      tcg_temp_free_i64(xbl);
>  }
>  
> -#define VSX_LOGICAL(name, tcg_op)                                    \
> +#define VSX_LOGICAL(name, vece, tcg_op)                              \
>  static void glue(gen_, name)(DisasContext * ctx)                     \
>      {                                                                \
> -        TCGv_i64 t0;                                                 \
> -        TCGv_i64 t1;                                                 \
> -        TCGv_i64 t2;                                                 \
>          if (unlikely(!ctx->vsx_enabled)) {                           \
>              gen_exception(ctx, POWERPC_EXCP_VSXU);                   \
>              return;                                                  \
>          }                                                            \
> -        t0 = tcg_temp_new_i64();                                     \
> -        t1 = tcg_temp_new_i64();                                     \
> -        t2 = tcg_temp_new_i64();                                     \
> -        get_cpu_vsrh(t0, xA(ctx->opcode));                           \
> -        get_cpu_vsrh(t1, xB(ctx->opcode));                           \
> -        tcg_op(t2, t0, t1);                                          \
> -        set_cpu_vsrh(xT(ctx->opcode), t2);                           \
> -        get_cpu_vsrl(t0, xA(ctx->opcode));                           \
> -        get_cpu_vsrl(t1, xB(ctx->opcode));                           \
> -        tcg_op(t2, t0, t1);                                          \
> -        set_cpu_vsrl(xT(ctx->opcode), t2);                           \
> -        tcg_temp_free_i64(t0);                                       \
> -        tcg_temp_free_i64(t1);                                       \
> -        tcg_temp_free_i64(t2);                                       \
> +        tcg_op(vece, vsr_full_offset(xT(ctx->opcode)),               \
> +               vsr_full_offset(xA(ctx->opcode)),                     \
> +               vsr_full_offset(xB(ctx->opcode)), 16, 16);            \
>      }
>  
> -VSX_LOGICAL(xxland, tcg_gen_and_i64)
> -VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
> -VSX_LOGICAL(xxlor, tcg_gen_or_i64)
> -VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
> -VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
> -VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
> -VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
> -VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
> +VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)
> +VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)
> +VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)
> +VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)
> +VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)
> +VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)
> +VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)
> +VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)
>  
>  #define VSX_XXMRG(name, high)                               \
>  static void glue(gen_, name)(DisasContext * ctx)            \

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2018-12-19  7:49 UTC|newest]

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-18  6:38 [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 01/34] tcg: Add logical simplifications during gvec expand Richard Henderson
2018-12-19  5:36   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or Richard Henderson
2018-12-19  5:37   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 03/34] tcg: Add gvec expanders for nand, nor, eqv Richard Henderson
2018-12-19  5:39   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 04/34] tcg: Add write_aofs to GVecGen4 Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 05/34] tcg: Add opcodes for vector saturated arithmetic Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 06/34] tcg/i386: Implement vector saturating arithmetic Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 07/34] tcg: Add opcodes for vector minmax arithmetic Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 08/34] tcg/i386: Implement " Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 09/34] target/arm: Use vector minmax expanders for aarch64 Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 10/34] target/arm: Use vector minmax expanders for aarch32 Richard Henderson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 11/34] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access Richard Henderson
2018-12-19  6:15   ` David Gibson
2018-12-19 12:29     ` Mark Cave-Ayland
2018-12-20 16:52       ` Mark Cave-Ayland
2018-12-18  6:38 ` [Qemu-devel] [PATCH 12/34] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX " Richard Henderson
2018-12-19  6:15   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 13/34] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR " Richard Henderson
2018-12-19  6:17   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env Richard Henderson
2018-12-19  6:20   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 15/34] target/ppc: merge ppc_vsr_t and ppc_avr_t union types Richard Henderson
2018-12-19  6:21   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 16/34] target/ppc: move FP and VMX registers into aligned vsr register array Richard Henderson
2018-12-19  6:27   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations Richard Henderson
2018-12-19  6:29   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 18/34] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over " Richard Henderson
2018-12-19  6:29   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] " Richard Henderson
2018-12-19  6:31   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 20/34] target/ppc: convert vsplt[bhw] " Richard Henderson
2018-12-19  6:32   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic " Richard Henderson
2018-12-19  6:32   ` David Gibson
2018-12-18  6:38 ` [Qemu-devel] [PATCH 22/34] target/ppc: convert VSX logical operations to " Richard Henderson
2018-12-19  6:33   ` David Gibson [this message]
2018-12-18  6:39 ` [Qemu-devel] [PATCH 23/34] target/ppc: convert xxspltib " Richard Henderson
2018-12-19  6:34   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw " Richard Henderson
2018-12-19  6:35   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel " Richard Henderson
2018-12-19  6:35   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 26/34] target/ppc: Pass integer to helper_mtvscr Richard Henderson
2018-12-19  6:37   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb Richard Henderson
2018-12-19  6:38   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 28/34] target/ppc: Remove vscr_nj and vscr_sat Richard Henderson
2018-12-19  6:38   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr Richard Henderson
2018-12-19  6:39   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 30/34] target/ppc: Use mtvscr/mfvscr for vmstate Richard Henderson
2018-12-19  6:40   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 31/34] target/ppc: Add set_vscr_sat Richard Henderson
2018-12-19  6:40   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field Richard Henderson
2018-12-19  6:41   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations Richard Henderson
2018-12-19  6:42   ` David Gibson
2018-12-18  6:39 ` [Qemu-devel] [PATCH 34/34] target/ppc: convert vmin* and vmax* " Richard Henderson
2018-12-19  6:42   ` David Gibson
2018-12-18  9:49 ` [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements Mark Cave-Ayland
2018-12-18 14:51   ` Mark Cave-Ayland
2018-12-18 15:07     ` Richard Henderson
2018-12-18 15:22       ` Mark Cave-Ayland
2018-12-18 15:05   ` Mark Cave-Ayland
2018-12-18 15:17     ` Richard Henderson
2018-12-18 15:26       ` Mark Cave-Ayland
2018-12-18 16:16         ` Richard Henderson
2019-01-03 14:58   ` Mark Cave-Ayland
2019-01-03 18:31 ` Mark Cave-Ayland
2019-01-04 22:33   ` Richard Henderson

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