From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
Alistair Francis <Alistair.Francis@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Michael Clark <mjc@sifive.com>
Subject: [Qemu-devel] [PULL 01/42] elf.h: Add the RISCV ELF magic numbers
Date: Wed, 26 Dec 2018 07:54:48 +1100 [thread overview]
Message-ID: <20181225205529.10874-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org>
From: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <02fc0b3a733f5f08eb396bee5afd3d327941f0c9.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/elf.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index c151164b63..0ac7911b7b 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1338,6 +1338,61 @@ typedef struct {
#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
+/* RISC-V relocations. */
+#define R_RISCV_NONE 0
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+#define R_RISCV_COPY 4
+#define R_RISCV_JUMP_SLOT 5
+#define R_RISCV_TLS_DTPMOD32 6
+#define R_RISCV_TLS_DTPMOD64 7
+#define R_RISCV_TLS_DTPREL32 8
+#define R_RISCV_TLS_DTPREL64 9
+#define R_RISCV_TLS_TPREL32 10
+#define R_RISCV_TLS_TPREL64 11
+#define R_RISCV_BRANCH 16
+#define R_RISCV_JAL 17
+#define R_RISCV_CALL 18
+#define R_RISCV_CALL_PLT 19
+#define R_RISCV_GOT_HI20 20
+#define R_RISCV_TLS_GOT_HI20 21
+#define R_RISCV_TLS_GD_HI20 22
+#define R_RISCV_PCREL_HI20 23
+#define R_RISCV_PCREL_LO12_I 24
+#define R_RISCV_PCREL_LO12_S 25
+#define R_RISCV_HI20 26
+#define R_RISCV_LO12_I 27
+#define R_RISCV_LO12_S 28
+#define R_RISCV_TPREL_HI20 29
+#define R_RISCV_TPREL_LO12_I 30
+#define R_RISCV_TPREL_LO12_S 31
+#define R_RISCV_TPREL_ADD 32
+#define R_RISCV_ADD8 33
+#define R_RISCV_ADD16 34
+#define R_RISCV_ADD32 35
+#define R_RISCV_ADD64 36
+#define R_RISCV_SUB8 37
+#define R_RISCV_SUB16 38
+#define R_RISCV_SUB32 39
+#define R_RISCV_SUB64 40
+#define R_RISCV_GNU_VTINHERIT 41
+#define R_RISCV_GNU_VTENTRY 42
+#define R_RISCV_ALIGN 43
+#define R_RISCV_RVC_BRANCH 44
+#define R_RISCV_RVC_JUMP 45
+#define R_RISCV_RVC_LUI 46
+#define R_RISCV_GPREL_I 47
+#define R_RISCV_GPREL_S 48
+#define R_RISCV_TPREL_I 49
+#define R_RISCV_TPREL_S 50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6 52
+#define R_RISCV_SET6 53
+#define R_RISCV_SET8 54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
+
typedef struct elf32_rel {
Elf32_Addr r_offset;
Elf32_Word r_info;
--
2.17.2
next prev parent reply other threads:[~2018-12-25 20:55 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-25 20:54 [Qemu-devel] [PULL 00/42] tcg queued patches Richard Henderson
2018-12-25 20:54 ` Richard Henderson [this message]
2018-12-25 20:54 ` [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct " Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 22/42] disas: Add RISC-V support Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 28/42] tcg: Reference count labels Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 32/42] tcg: Add preferred_reg argument to temp_sync Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 34/42] tcg: Add output_pref to TCGOp Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 35/42] tcg: Improve register allocation for matching constraints Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 36/42] tcg: Dump register preference info with liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 37/42] tcg: Reindent parts of liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 38/42] tcg: Rename and adjust liveness_pass_1 helpers Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 39/42] tcg: Split out more subroutines from liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 40/42] tcg: Add TCG_OPF_BB_EXIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 41/42] tcg: Record register preferences during liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 42/42] tcg: Improve call argument loading Richard Henderson
2019-01-02 22:32 ` [Qemu-devel] [PULL 00/42] tcg queued patches no-reply
2019-01-03 11:59 ` Peter Maydell
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