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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host
Date: Wed, 26 Dec 2018 07:55:12 +1100	[thread overview]
Message-ID: <20181225205529.10874-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 linux-user/host/riscv64/hostdep.h          | 23 +++++++
 linux-user/host/riscv64/safe-syscall.inc.S | 77 ++++++++++++++++++++++
 2 files changed, 100 insertions(+)
 create mode 100644 linux-user/host/riscv64/safe-syscall.inc.S

diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv64/hostdep.h
index 28467ba00b..865f0fb9ff 100644
--- a/linux-user/host/riscv64/hostdep.h
+++ b/linux-user/host/riscv64/hostdep.h
@@ -8,4 +8,27 @@
 #ifndef RISCV64_HOSTDEP_H
 #define RISCV64_HOSTDEP_H
 
+/* We have a safe-syscall.inc.S */
+#define HAVE_SAFE_SYSCALL
+
+#ifndef __ASSEMBLER__
+
+/* These are defined by the safe-syscall.inc.S file */
+extern char safe_syscall_start[];
+extern char safe_syscall_end[];
+
+/* Adjust the signal context to rewind out of safe-syscall if we're in it */
+static inline void rewind_if_in_safe_syscall(void *puc)
+{
+    ucontext_t *uc = puc;
+    unsigned long *pcreg = &uc->uc_mcontext.__gregs[REG_PC];
+
+    if (*pcreg > (uintptr_t)safe_syscall_start
+        && *pcreg < (uintptr_t)safe_syscall_end) {
+        *pcreg = (uintptr_t)safe_syscall_start;
+    }
+}
+
+#endif /* __ASSEMBLER__ */
+
 #endif
diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv64/safe-syscall.inc.S
new file mode 100644
index 0000000000..9ca3fbfd1e
--- /dev/null
+++ b/linux-user/host/riscv64/safe-syscall.inc.S
@@ -0,0 +1,77 @@
+/*
+ * safe-syscall.inc.S : host-specific assembly fragment
+ * to handle signals occurring at the same time as system calls.
+ * This is intended to be included by linux-user/safe-syscall.S
+ *
+ * Written by Richard Henderson <rth@twiddle.net>
+ * Copyright (C) 2018 Linaro, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+	.global safe_syscall_base
+	.global safe_syscall_start
+	.global safe_syscall_end
+	.type	safe_syscall_base, @function
+	.type	safe_syscall_start, @function
+	.type	safe_syscall_end, @function
+
+	/*
+	 * This is the entry point for making a system call. The calling
+	 * convention here is that of a C varargs function with the
+	 * first argument an 'int *' to the signal_pending flag, the
+	 * second one the system call number (as a 'long'), and all further
+	 * arguments being syscall arguments (also 'long').
+	 * We return a long which is the syscall's return value, which
+	 * may be negative-errno on failure. Conversion to the
+	 * -1-and-errno-set convention is done by the calling wrapper.
+	 */
+safe_syscall_base:
+	.cfi_startproc
+	/*
+	 * The syscall calling convention is nearly the same as C:
+	 * we enter with a0 == *signal_pending
+	 *               a1 == syscall number
+	 *               a2 ... a7 == syscall arguments
+	 *               and return the result in a0
+	 * and the syscall instruction needs
+	 *               a7 == syscall number
+	 *               a0 ... a5 == syscall arguments
+	 *               and returns the result in a0
+	 * Shuffle everything around appropriately.
+	 */
+	mv	t0, a0		/* signal_pending pointer */
+	mv	t1, a1		/* syscall number */
+	mv	a0, a2		/* syscall arguments */
+	mv	a1, a3
+	mv	a2, a4
+	mv	a3, a5
+	mv	a4, a6
+	mv	a5, a7
+	mv	a7, t1
+
+	/*
+	 * This next sequence of code works in conjunction with the
+	 * rewind_if_safe_syscall_function(). If a signal is taken
+	 * and the interrupted PC is anywhere between 'safe_syscall_start'
+	 * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'.
+	 * The code sequence must therefore be able to cope with this, and
+	 * the syscall instruction must be the final one in the sequence.
+	 */
+safe_syscall_start:
+	/* If signal_pending is non-zero, don't do the call */
+	lw	t1, 0(t0)
+	bnez	t1, 0f
+	scall
+safe_syscall_end:
+	/* code path for having successfully executed the syscall */
+	ret
+
+0:
+	/* code path when we didn't execute the syscall */
+	li	a0, -TARGET_ERESTARTSYS
+	ret
+	.cfi_endproc
+
+	.size	safe_syscall_base, .-safe_syscall_base
-- 
2.17.2

  parent reply	other threads:[~2018-12-25 20:58 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-25 20:54 [Qemu-devel] [PULL 00/42] tcg queued patches Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 01/42] elf.h: Add the RISCV ELF magic numbers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct " Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 22/42] disas: Add RISC-V support Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro Richard Henderson
2018-12-25 20:55 ` Richard Henderson [this message]
2018-12-25 20:55 ` [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 28/42] tcg: Reference count labels Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 32/42] tcg: Add preferred_reg argument to temp_sync Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 34/42] tcg: Add output_pref to TCGOp Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 35/42] tcg: Improve register allocation for matching constraints Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 36/42] tcg: Dump register preference info with liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 37/42] tcg: Reindent parts of liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 38/42] tcg: Rename and adjust liveness_pass_1 helpers Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 39/42] tcg: Split out more subroutines from liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 40/42] tcg: Add TCG_OPF_BB_EXIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 41/42] tcg: Record register preferences during liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 42/42] tcg: Improve call argument loading Richard Henderson
2019-01-02 22:32 ` [Qemu-devel] [PULL 00/42] tcg queued patches no-reply
2019-01-03 11:59 ` Peter Maydell

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