qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc
Date: Wed, 26 Dec 2018 07:55:17 +1100	[thread overview]
Message-ID: <20181225205529.10874-31-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org>

This new argument will aid register allocation by indicating how
the temporary will be used in future.  If the preference cannot
be satisfied, fall back to the constraints of the current insn.

Short circuit the preference when it cannot be satisfied or if
it does not further constrain the operation.

With an eye toward optimizing function call sequences, optimize
for the preferred_reg set containing a single register.

For the moment, all users pass 0 for preference.

Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c | 103 ++++++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 81 insertions(+), 22 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index d2be550ab4..210bd5c6b9 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1887,6 +1887,20 @@ static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = {
     [MO_ALIGN_64 >> MO_ASHIFT] = "al64+",
 };
 
+static inline bool tcg_regset_single(TCGRegSet d)
+{
+    return (d & (d - 1)) == 0;
+}
+
+static inline TCGReg tcg_regset_first(TCGRegSet d)
+{
+    if (TCG_TARGET_NB_REGS <= 32) {
+        return ctz32(d);
+    } else {
+        return ctz64(d);
+    }
+}
+
 void tcg_dump_ops(TCGContext *s)
 {
     char buf[128];
@@ -1902,6 +1916,7 @@ void tcg_dump_ops(TCGContext *s)
         def = &tcg_op_defs[c];
 
         if (c == INDEX_op_insn_start) {
+            nb_oargs = 0;
             col += qemu_log("\n ----");
 
             for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
@@ -2902,31 +2917,72 @@ static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs)
     }
 }
 
-/* Allocate a register belonging to reg1 & ~reg2 */
-static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs,
-                            TCGRegSet allocated_regs, bool rev)
+/**
+ * tcg_reg_alloc:
+ * @required_regs: Set of registers in which we must allocate.
+ * @allocated_regs: Set of registers which must be avoided.
+ * @preferred_regs: Set of registers we should prefer.
+ * @rev: True if we search the registers in "indirect" order.
+ *
+ * The allocated register must be in @required_regs & ~@allocated_regs,
+ * but if we can put it in @preferred_regs we may save a move later.
+ */
+static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs,
+                            TCGRegSet allocated_regs,
+                            TCGRegSet preferred_regs, bool rev)
 {
-    int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order);
+    int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order);
+    TCGRegSet reg_ct[2];
     const int *order;
-    TCGReg reg;
-    TCGRegSet reg_ct;
 
-    reg_ct = desired_regs & ~allocated_regs;
+    reg_ct[1] = required_regs & ~allocated_regs;
+    tcg_debug_assert(reg_ct[1] != 0);
+    reg_ct[0] = reg_ct[1] & preferred_regs;
+
+    /* Skip the preferred_regs option if it cannot be satisfied,
+       or if the preference made no difference.  */
+    f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1];
+
     order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;
 
-    /* first try free registers */
-    for(i = 0; i < n; i++) {
-        reg = order[i];
-        if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL)
-            return reg;
+    /* Try free registers, preferences first.  */
+    for (j = f; j < 2; j++) {
+        TCGRegSet set = reg_ct[j];
+
+        if (tcg_regset_single(set)) {
+            /* One register in the set.  */
+            TCGReg reg = tcg_regset_first(set);
+            if (s->reg_to_temp[reg] == NULL) {
+                return reg;
+            }
+        } else {
+            for (i = 0; i < n; i++) {
+                TCGReg reg = order[i];
+                if (s->reg_to_temp[reg] == NULL &&
+                    tcg_regset_test_reg(set, reg)) {
+                    return reg;
+                }
+            }
+        }
     }
 
-    /* XXX: do better spill choice */
-    for(i = 0; i < n; i++) {
-        reg = order[i];
-        if (tcg_regset_test_reg(reg_ct, reg)) {
+    /* We must spill something.  */
+    for (j = f; j < 2; j++) {
+        TCGRegSet set = reg_ct[j];
+
+        if (tcg_regset_single(set)) {
+            /* One register in the set.  */
+            TCGReg reg = tcg_regset_first(set);
             tcg_reg_free(s, reg, allocated_regs);
             return reg;
+        } else {
+            for (i = 0; i < n; i++) {
+                TCGReg reg = order[i];
+                if (tcg_regset_test_reg(set, reg)) {
+                    tcg_reg_free(s, reg, allocated_regs);
+                    return reg;
+                }
+            }
         }
     }
 
@@ -2944,12 +3000,14 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
     case TEMP_VAL_REG:
         return;
     case TEMP_VAL_CONST:
-        reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base);
+        reg = tcg_reg_alloc(s, desired_regs, allocated_regs,
+                            0, ts->indirect_base);
         tcg_out_movi(s, ts->type, reg, ts->val);
         ts->mem_coherent = 0;
         break;
     case TEMP_VAL_MEM:
-        reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base);
+        reg = tcg_reg_alloc(s, desired_regs, allocated_regs,
+                            0, ts->indirect_base);
         tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset);
         ts->mem_coherent = 1;
         break;
@@ -3109,7 +3167,8 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
                    input one. */
                 tcg_regset_set_reg(allocated_regs, ts->reg);
                 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
-                                         allocated_regs, ots->indirect_base);
+                                         allocated_regs, 0,
+                                         ots->indirect_base);
             }
             tcg_out_mov(s, otype, ots->reg, ts->reg);
         }
@@ -3197,7 +3256,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             /* allocate a new register matching the constraint 
                and move the temporary register into it */
             reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
-                                ts->indirect_base);
+                                0, ts->indirect_base);
             tcg_out_mov(s, ts->type, reg, ts->reg);
         }
         new_args[i] = reg;
@@ -3242,7 +3301,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             } else if (arg_ct->ct & TCG_CT_NEWREG) {
                 reg = tcg_reg_alloc(s, arg_ct->u.regs,
                                     i_allocated_regs | o_allocated_regs,
-                                    ts->indirect_base);
+                                    0, ts->indirect_base);
             } else {
                 /* if fixed register, we try to use it */
                 reg = ts->reg;
@@ -3251,7 +3310,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                     goto oarg_end;
                 }
                 reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
-                                    ts->indirect_base);
+                                    0, ts->indirect_base);
             }
             tcg_regset_set_reg(o_allocated_regs, reg);
             /* if a fixed register is used, then a move will be done afterwards */
-- 
2.17.2

  parent reply	other threads:[~2018-12-25 20:59 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-25 20:54 [Qemu-devel] [PULL 00/42] tcg queued patches Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 01/42] elf.h: Add the RISCV ELF magic numbers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct " Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 22/42] disas: Add RISC-V support Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 28/42] tcg: Reference count labels Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass Richard Henderson
2018-12-25 20:55 ` Richard Henderson [this message]
2018-12-25 20:55 ` [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 32/42] tcg: Add preferred_reg argument to temp_sync Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 34/42] tcg: Add output_pref to TCGOp Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 35/42] tcg: Improve register allocation for matching constraints Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 36/42] tcg: Dump register preference info with liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 37/42] tcg: Reindent parts of liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 38/42] tcg: Rename and adjust liveness_pass_1 helpers Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 39/42] tcg: Split out more subroutines from liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 40/42] tcg: Add TCG_OPF_BB_EXIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 41/42] tcg: Record register preferences during liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 42/42] tcg: Improve call argument loading Richard Henderson
2019-01-02 22:32 ` [Qemu-devel] [PULL 00/42] tcg queued patches no-reply
2019-01-03 11:59 ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181225205529.10874-31-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).