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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 32/42] tcg: Add preferred_reg argument to temp_sync
Date: Wed, 26 Dec 2018 07:55:19 +1100	[thread overview]
Message-ID: <20181225205529.10874-33-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org>

Pass this through to tcg_reg_alloc.

Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index 351d302a68..fe060c481a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2865,8 +2865,8 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts)
    registers needs to be allocated to store a constant.  If 'free_or_dead'
    is non-zero, subsequently release the temporary; if it is positive, the
    temp is dead; if it is negative, the temp is free.  */
-static void temp_sync(TCGContext *s, TCGTemp *ts,
-                      TCGRegSet allocated_regs, int free_or_dead)
+static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs,
+                      TCGRegSet preferred_regs, int free_or_dead)
 {
     if (ts->fixed_reg) {
         return;
@@ -2886,7 +2886,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts,
                 break;
             }
             temp_load(s, ts, tcg_target_available_regs[ts->type],
-                      allocated_regs, 0);
+                      allocated_regs, preferred_regs);
             /* fallthrough */
 
         case TEMP_VAL_REG:
@@ -2913,7 +2913,7 @@ static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs)
 {
     TCGTemp *ts = s->reg_to_temp[reg];
     if (ts != NULL) {
-        temp_sync(s, ts, allocated_regs, -1);
+        temp_sync(s, ts, allocated_regs, 0, -1);
     }
 }
 
@@ -3093,7 +3093,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
     ots->val = val;
     ots->mem_coherent = 0;
     if (NEED_SYNC_ARG(0)) {
-        temp_sync(s, ots, s->reserved_regs, IS_DEAD_ARG(0));
+        temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0));
     } else if (IS_DEAD_ARG(0)) {
         temp_dead(s, ots);
     }
@@ -3176,7 +3176,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
         ots->mem_coherent = 0;
         s->reg_to_temp[ots->reg] = ots;
         if (NEED_SYNC_ARG(0)) {
-            temp_sync(s, ots, allocated_regs, 0);
+            temp_sync(s, ots, allocated_regs, 0, 0);
         }
     }
 }
@@ -3346,7 +3346,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             tcg_out_mov(s, ts->type, ts->reg, reg);
         }
         if (NEED_SYNC_ARG(i)) {
-            temp_sync(s, ts, o_allocated_regs, IS_DEAD_ARG(i));
+            temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i));
         } else if (IS_DEAD_ARG(i)) {
             temp_dead(s, ts);
         }
@@ -3480,7 +3480,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
             ts->mem_coherent = 0;
             s->reg_to_temp[reg] = ts;
             if (NEED_SYNC_ARG(i)) {
-                temp_sync(s, ts, allocated_regs, IS_DEAD_ARG(i));
+                temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i));
             } else if (IS_DEAD_ARG(i)) {
                 temp_dead(s, ts);
             }
-- 
2.17.2

  parent reply	other threads:[~2018-12-25 20:59 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-25 20:54 [Qemu-devel] [PULL 00/42] tcg queued patches Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 01/42] elf.h: Add the RISCV ELF magic numbers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction Richard Henderson
2018-12-25 20:54 ` [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct " Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 22/42] disas: Add RISC-V support Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 28/42] tcg: Reference count labels Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load Richard Henderson
2018-12-25 20:55 ` Richard Henderson [this message]
2018-12-25 20:55 ` [Qemu-devel] [PULL 33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 34/42] tcg: Add output_pref to TCGOp Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 35/42] tcg: Improve register allocation for matching constraints Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 36/42] tcg: Dump register preference info with liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 37/42] tcg: Reindent parts of liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 38/42] tcg: Rename and adjust liveness_pass_1 helpers Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 39/42] tcg: Split out more subroutines from liveness_pass_1 Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 40/42] tcg: Add TCG_OPF_BB_EXIT Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 41/42] tcg: Record register preferences during liveness Richard Henderson
2018-12-25 20:55 ` [Qemu-devel] [PULL 42/42] tcg: Improve call argument loading Richard Henderson
2019-01-02 22:32 ` [Qemu-devel] [PULL 00/42] tcg queued patches no-reply
2019-01-03 11:59 ` Peter Maydell

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