From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gcCrN-0004EG-Fj for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gcCrH-0007rw-M3 for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:41 -0500 Received: from mail-qk1-x744.google.com ([2607:f8b0:4864:20::744]:36998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gcCrD-0007mx-P4 for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:36 -0500 Received: by mail-qk1-x744.google.com with SMTP id g125so9624166qke.4 for ; Wed, 26 Dec 2018 09:20:30 -0800 (PST) Date: Wed, 26 Dec 2018 09:20:00 -0800 Message-Id: <20181226172005.26990-10-palmer@sifive.com> In-Reply-To: <20181226172005.26990-1-palmer@sifive.com> References: <20181226172005.26990-1-palmer@sifive.com> From: Palmer Dabbelt Subject: [Qemu-devel] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , Alistair Francis , Alistair Francis From: Michael Clark The address calculation for the pending bitfield had a copy paste bug. This bug went unnoticed because the Linux PLIC driver does not read the pending bitfield, rather it reads pending interrupt numbers from the claim register and writes acknowledgements back to the claim register. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Reported-by: Vincent Siles Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_plic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 9cf9a1f98644..d12ec3fc9a54 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -214,7 +214,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) } else if (addr >= plic->pending_base && /* 1 bit per source */ addr < plic->pending_base + (plic->num_sources >> 3)) { - uint32_t word = (addr - plic->priority_base) >> 2; + uint32_t word = (addr - plic->pending_base) >> 2; if (RISCV_DEBUG_PLIC) { qemu_log("plic: read pending: word=%d value=%d\n", word, plic->pending[word]); -- 2.18.1