From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported
Date: Wed, 26 Dec 2018 09:20:05 -0800 [thread overview]
Message-ID: <20181226172005.26990-15-palmer@sifive.com> (raw)
In-Reply-To: <20181226172005.26990-1-palmer@sifive.com>
There's at least two of us that are paid to work on this.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d676c73f8840..317eff6cec4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -262,7 +262,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
M: Sagar Karandikar <sagark@eecs.berkeley.edu>
M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
L: qemu-riscv@nongnu.org
-S: Maintained
+S: Supported
F: target/riscv/
F: hw/riscv/
F: include/hw/riscv/
--
2.18.1
next prev parent reply other threads:[~2018-12-26 17:20 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-26 17:19 [Qemu-devel] [PULL] RISC-V Changes for 3.2, Part 1 Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 04/14] riscv: Enable VGA and PCIE_VGA Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 11/14] sifive_uart: Implement interrupt pending register Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize Palmer Dabbelt
2018-12-26 17:20 ` Palmer Dabbelt [this message]
2019-01-03 16:46 ` [Qemu-devel] [PULL] RISC-V Changes for 3.2, Part 1 Peter Maydell
2019-01-08 19:37 ` [Qemu-devel] Wiki Account Creation [Was Re: [PULL] RISC-V Changes for 3.2, Part 1] Palmer Dabbelt
2019-01-08 20:35 ` Max Filippov
2019-01-09 19:37 ` Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2018-12-21 16:02 [Qemu-devel] [PR RFC] RISC-V Changes for 3.2, Part 1 Palmer Dabbelt
2018-12-21 16:03 ` [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported Palmer Dabbelt
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