From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 03/10] ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU
Date: Wed, 2 Jan 2019 06:57:36 +0100 [thread overview]
Message-ID: <20190102055743.5052-4-clg@kaod.org> (raw)
In-Reply-To: <20190102055743.5052-1-clg@kaod.org>
Now that the 'intc' pointer is only used by the XICS interrupt mode,
let's make things clear and use a XICS type and name.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 3 ++-
hw/intc/xics_spapr.c | 10 +++++-----
hw/ppc/pnv.c | 6 +++---
hw/ppc/pnv_core.c | 2 +-
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_cpu_core.c | 4 ++--
hw/ppc/spapr_irq.c | 6 +++---
7 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c76036985623..757606bcb2e2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1178,6 +1178,7 @@ do { \
typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
typedef struct XiveTCTX XiveTCTX;
+typedef struct ICPState ICPState;
/**
* PowerPCCPU:
@@ -1196,7 +1197,7 @@ struct PowerPCCPU {
int vcpu_id;
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
- Object *intc;
+ ICPState *icp;
XiveTCTX *tctx;
void *machine_data;
int32_t node_id; /* NUMA node this CPU belongs to */
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index f67d3c80bf3a..9c1a90d7094b 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -44,7 +44,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
{
target_ulong cppr = args[0];
- icp_set_cppr(ICP(cpu->intc), cppr);
+ icp_set_cppr(cpu->icp, cppr);
return H_SUCCESS;
}
@@ -65,7 +65,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- uint32_t xirr = icp_accept(ICP(cpu->intc));
+ uint32_t xirr = icp_accept(cpu->icp);
args[0] = xirr;
return H_SUCCESS;
@@ -74,7 +74,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- uint32_t xirr = icp_accept(ICP(cpu->intc));
+ uint32_t xirr = icp_accept(cpu->icp);
args[0] = xirr;
args[1] = cpu_get_host_ticks();
@@ -86,7 +86,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
{
target_ulong xirr = args[0];
- icp_eoi(ICP(cpu->intc), xirr);
+ icp_eoi(cpu->icp, xirr);
return H_SUCCESS;
}
@@ -94,7 +94,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
uint32_t mfrr;
- uint32_t xirr = icp_ipoll(ICP(cpu->intc), &mfrr);
+ uint32_t xirr = icp_ipoll(cpu->icp, &mfrr);
args[0] = xirr;
args[1] = mfrr;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8e83be54fca1..d84acef55b69 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -681,7 +681,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
return;
}
- cpu->intc = obj;
+ cpu->icp = ICP(obj);
}
/*
@@ -1099,7 +1099,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
{
PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
- return cpu ? ICP(cpu->intc) : NULL;
+ return cpu ? cpu->icp : NULL;
}
static void pnv_pic_print_info(InterruptStatsProvider *obj,
@@ -1112,7 +1112,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_pic_print_info(ICP(cpu->intc), mon);
+ icp_pic_print_info(cpu->icp, mon);
}
for (i = 0; i < pnv->num_chips; i++) {
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 120273774874..b98f277f1e02 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -190,7 +190,7 @@ err:
static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
{
qemu_unregister_reset(pnv_cpu_reset, cpu);
- object_unparent(cpu->intc);
+ object_unparent(OBJECT(cpu->icp));
cpu_remove_sync(CPU(cpu));
object_unparent(OBJECT(cpu));
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 19a07c5c9dd8..5e8ffda47372 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3841,7 +3841,7 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
{
PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
- return cpu ? ICP(cpu->intc) : NULL;
+ return cpu ? cpu->icp : NULL;
}
static void spapr_pic_print_info(InterruptStatsProvider *obj,
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 1473ef853336..0405306d1e59 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -194,8 +194,8 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
}
qemu_unregister_reset(spapr_cpu_reset, cpu);
- if (cpu->intc) {
- object_unparent(cpu->intc);
+ if (cpu->icp) {
+ object_unparent(OBJECT(cpu->icp));
}
if (cpu->tctx) {
object_unparent(OBJECT(cpu->tctx));
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 8d028db44ff4..50e767120d21 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -184,7 +184,7 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_pic_print_info(ICP(cpu->intc), mon);
+ icp_pic_print_info(cpu->icp, mon);
}
ics_pic_print_info(spapr->ics, mon);
@@ -203,7 +203,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
return;
}
- cpu->intc = obj;
+ cpu->icp = ICP(obj);
}
static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
@@ -212,7 +212,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_resend(ICP(cpu->intc));
+ icp_resend(cpu->icp);
}
}
return 0;
--
2.20.1
next prev parent reply other threads:[~2019-01-02 5:58 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-02 5:57 [Qemu-devel] [PATCH 00/10] spapr: introduce the 'dual' interrupt mode XICS/XIVE Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 01/10] spapr: modify the prototype of the cpu_intc_create() method Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 02/10] ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU Cédric Le Goater
2019-01-03 3:57 ` David Gibson
2019-01-03 17:44 ` Cédric Le Goater
2019-01-04 5:25 ` David Gibson
2019-01-02 5:57 ` Cédric Le Goater [this message]
2019-01-02 5:57 ` [Qemu-devel] [PATCH 04/10] spapr/xive: simplify the sPAPR IRQ qirq method for XIVE Cédric Le Goater
2019-01-03 3:58 ` David Gibson
2019-01-02 5:57 ` [Qemu-devel] [PATCH 05/10] ppc: export the XICS and XIVE set_irq handlers Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 06/10] pnv/psi: move the ICSState qemu_irq array under the PSI device model Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 07/10] spapr: move the qemu_irq array under the machine Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 08/10] ppc/xics: allow ICSState to have an offset 0 Cédric Le Goater
2019-01-03 4:33 ` David Gibson
2019-01-03 17:45 ` Cédric Le Goater
2019-01-07 4:29 ` David Gibson
2019-01-02 5:57 ` [Qemu-devel] [PATCH 09/10] spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS Cédric Le Goater
2019-01-03 4:35 ` David Gibson
2019-01-03 17:45 ` Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 10/10] spapr: enable XIVE MMIOs at reset Cédric Le Goater
2019-01-07 4:48 ` [Qemu-devel] [PATCH 00/10] spapr: introduce the 'dual' interrupt mode XICS/XIVE David Gibson
2019-01-07 6:54 ` Cédric Le Goater
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