From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 08/10] ppc/xics: allow ICSState to have an offset 0
Date: Thu, 3 Jan 2019 15:33:40 +1100 [thread overview]
Message-ID: <20190103043340.GT10853@umbus.fritz.box> (raw)
In-Reply-To: <20190102055743.5052-9-clg@kaod.org>
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On Wed, Jan 02, 2019 at 06:57:41AM +0100, Cédric Le Goater wrote:
> commit 15ed653fa49a ("ppc/xics: An ICS with offset 0 is assumed to be
> uninitialized") introduced an extra check on the ICS offset which is
> not strictly necessary.
The commit message for that suggests it was added to make pnv easier.
I take it you no longer need this for the current or expected pnv
code?
> Revert the change to be able to map the XICS IRQ number space on the
> XIVE IRQ number space.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/ppc/xics.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 7668c381a887..07508cbd217e 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -139,8 +139,7 @@ struct ICSState {
>
> static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
> {
> - return (ics->offset != 0) && (nr >= ics->offset)
> - && (nr < (ics->offset + ics->nr_irqs));
> + return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
> }
>
> struct ICSIRQState {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2019-01-03 4:58 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-02 5:57 [Qemu-devel] [PATCH 00/10] spapr: introduce the 'dual' interrupt mode XICS/XIVE Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 01/10] spapr: modify the prototype of the cpu_intc_create() method Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 02/10] ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU Cédric Le Goater
2019-01-03 3:57 ` David Gibson
2019-01-03 17:44 ` Cédric Le Goater
2019-01-04 5:25 ` David Gibson
2019-01-02 5:57 ` [Qemu-devel] [PATCH 03/10] ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 04/10] spapr/xive: simplify the sPAPR IRQ qirq method for XIVE Cédric Le Goater
2019-01-03 3:58 ` David Gibson
2019-01-02 5:57 ` [Qemu-devel] [PATCH 05/10] ppc: export the XICS and XIVE set_irq handlers Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 06/10] pnv/psi: move the ICSState qemu_irq array under the PSI device model Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 07/10] spapr: move the qemu_irq array under the machine Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 08/10] ppc/xics: allow ICSState to have an offset 0 Cédric Le Goater
2019-01-03 4:33 ` David Gibson [this message]
2019-01-03 17:45 ` Cédric Le Goater
2019-01-07 4:29 ` David Gibson
2019-01-02 5:57 ` [Qemu-devel] [PATCH 09/10] spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS Cédric Le Goater
2019-01-03 4:35 ` David Gibson
2019-01-03 17:45 ` Cédric Le Goater
2019-01-02 5:57 ` [Qemu-devel] [PATCH 10/10] spapr: enable XIVE MMIOs at reset Cédric Le Goater
2019-01-07 4:48 ` [Qemu-devel] [PATCH 00/10] spapr: introduce the 'dual' interrupt mode XICS/XIVE David Gibson
2019-01-07 6:54 ` Cédric Le Goater
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