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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 35/37] target/arm: Emit barriers for A32/T32 load-acquire/store-release insns
Date: Mon,  7 Jan 2019 16:31:15 +0000	[thread overview]
Message-ID: <20190107163117.16269-36-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org>

Now that MTTCG is here, the comment in the 32-bit Arm decoder that
"Since the emulation does not have barriers, the acquire/release
semantics need no special handling" is no longer true. Emit the
correct barriers for the load-acquire/store-release insns, as
we already do in the A64 decoder.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 target/arm/translate.c | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index ed3db0c3946..66cf28c8cbe 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9733,6 +9733,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     rd = (insn >> 12) & 0xf;
                     if (insn & (1 << 23)) {
                         /* load/store exclusive */
+                        bool is_ld = extract32(insn, 20, 1);
+                        bool is_lasr = !extract32(insn, 8, 1);
                         int op2 = (insn >> 8) & 3;
                         op1 = (insn >> 21) & 0x3;
 
@@ -9760,11 +9762,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                         addr = tcg_temp_local_new_i32();
                         load_reg_var(s, addr, rn);
 
-                        /* Since the emulation does not have barriers,
-                           the acquire/release semantics need no special
-                           handling */
+                        if (is_lasr && !is_ld) {
+                            tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+                        }
+
                         if (op2 == 0) {
-                            if (insn & (1 << 20)) {
+                            if (is_ld) {
                                 tmp = tcg_temp_new_i32();
                                 switch (op1) {
                                 case 0: /* lda */
@@ -9810,7 +9813,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                 }
                                 tcg_temp_free_i32(tmp);
                             }
-                        } else if (insn & (1 << 20)) {
+                        } else if (is_ld) {
                             switch (op1) {
                             case 0: /* ldrex */
                                 gen_load_exclusive(s, rd, 15, addr, 2);
@@ -9847,6 +9850,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                             }
                         }
                         tcg_temp_free_i32(addr);
+
+                        if (is_lasr && is_ld) {
+                            tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+                        }
                     } else if ((insn & 0x00300f00) == 0) {
                         /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
                         *  - SWP, SWPB
@@ -10862,6 +10869,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 tcg_gen_addi_i32(tmp, tmp, s->pc);
                 store_reg(s, 15, tmp);
             } else {
+                bool is_lasr = false;
+                bool is_ld = extract32(insn, 20, 1);
                 int op2 = (insn >> 6) & 0x3;
                 op = (insn >> 4) & 0x3;
                 switch (op2) {
@@ -10883,12 +10892,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 case 3:
                     /* Load-acquire/store-release exclusive */
                     ARCH(8);
+                    is_lasr = true;
                     break;
                 }
+
+                if (is_lasr && !is_ld) {
+                    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+                }
+
                 addr = tcg_temp_local_new_i32();
                 load_reg_var(s, addr, rn);
                 if (!(op2 & 1)) {
-                    if (insn & (1 << 20)) {
+                    if (is_ld) {
                         tmp = tcg_temp_new_i32();
                         switch (op) {
                         case 0: /* ldab */
@@ -10927,12 +10942,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                         }
                         tcg_temp_free_i32(tmp);
                     }
-                } else if (insn & (1 << 20)) {
+                } else if (is_ld) {
                     gen_load_exclusive(s, rs, rd, addr, op);
                 } else {
                     gen_store_exclusive(s, rm, rs, rd, addr, op);
                 }
                 tcg_temp_free_i32(addr);
+
+                if (is_lasr && is_ld) {
+                    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+                }
             }
         } else {
             /* Load/store multiple, RFE, SRS.  */
-- 
2.19.2

  parent reply	other threads:[~2019-01-07 16:32 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-07 16:30 [Qemu-devel] [PULL 00/37] target-arm queue Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 01/37] target/arm: Convert ARM_TBFLAG_* to FIELDs Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 02/37] target/arm: SVE brk[ab] merging does not have s bit Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 03/37] hw/cpu: introduce CPU clusters Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 04/37] gdbstub: introduce GDB processes Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 05/37] gdbstub: add multiprocess support to '?' packets Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 06/37] gdbstub: add multiprocess support to 'H' and 'T' packets Peter Maydell
2019-01-17 18:13   ` Peter Maydell
2019-01-17 18:19     ` Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 07/37] gdbstub: add multiprocess support to vCont packets Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 08/37] gdbstub: add multiprocess support to 'sC' packets Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 09/37] gdbstub: add multiprocess support to (f|s)ThreadInfo and ThreadExtraInfo Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 10/37] gdbstub: add multiprocess support to Xfer:features:read: Peter Maydell
2019-01-17 17:22   ` Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 11/37] gdbstub: add multiprocess support to gdb_vm_state_change() Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 12/37] gdbstub: add multiprocess support to 'D' packets Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 13/37] gdbstub: add support for extended mode packet Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 14/37] gdbstub: add support for vAttach packets Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 15/37] gdbstub: processes initialization on new peer connection Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 16/37] gdbstub: gdb_set_stop_cpu: ignore request when process is not attached Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 17/37] gdbstub: add multiprocess extension support Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 18/37] arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters Peter Maydell
2019-01-07 16:30 ` [Qemu-devel] [PULL 19/37] Revert "armv7m: Guard against no -kernel argument" Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 20/37] hw/arm: versal: Plug memory leaks Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 21/37] MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/ Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 22/37] cpus.c: Fix race condition in cpu_stop_current() Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 23/37] hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 24/37] qtest: Add set_irq_in command to set IRQ/GPIO level Peter Maydell
2019-01-09  5:58   ` Matthew Ogilvie
2019-01-10 15:53     ` Peter Maydell
2019-01-10 16:26       ` Eric Blake
2019-01-07 16:31 ` [Qemu-devel] [PULL 25/37] arm: Add header to host common definition for nRF51 SOC peripherals Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 26/37] hw/misc/nrf51_rng: Add NRF51 random number generator peripheral Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 27/37] arm: Instantiate NRF51 random number generator Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 28/37] hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 29/37] arm: Instantiate NRF51 general purpose I/O Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 30/37] tests/microbit-test: Add Tests for nRF51 GPIO Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 31/37] hw/timer/nrf51_timer: Add nRF51 Timer peripheral Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 32/37] arm: Instantiate NRF51 Timers Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 33/37] tests/microbit-test: Add Tests for nRF51 Timer Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 34/37] arm: Add Clock peripheral stub to NRF51 SOC Peter Maydell
2019-01-07 16:31 ` Peter Maydell [this message]
2019-01-07 16:31 ` [Qemu-devel] [PULL 36/37] hw/misc/tz-mpc: Fix value of BLK_MAX register Peter Maydell
2019-01-07 16:31 ` [Qemu-devel] [PULL 37/37] Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel Peter Maydell
2019-01-07 18:24 ` [Qemu-devel] [PULL 00/37] target-arm queue Peter Maydell
2019-01-07 20:29 ` no-reply

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