From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v3 30/31] target/arm: Enable PAuth for user-only
Date: Wed, 9 Jan 2019 08:31:28 +1000 [thread overview]
Message-ID: <20190108223129.5570-31-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org>
Add 4 attributes that controls the EL1 enable bits, as we may not
always want to turn on pointer authentication with -cpu max.
However, by default they are enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 3 +++
target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4c4e9e169e..14bc24a35a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -162,6 +162,9 @@ static void arm_cpu_reset(CPUState *s)
env->pstate = PSTATE_MODE_EL0t;
/* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
+ /* Enable all PAC instructions */
+ env->cp15.hcr_el2 |= HCR_API;
+ env->cp15.scr_el3 |= SCR_API;
/* and to the FP/Neon instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
/* and to the SVE instructions */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1974f1aeb7..d0de0d5dcf 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -285,6 +285,38 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
error_propagate(errp, err);
}
+#ifdef CONFIG_USER_ONLY
+static void cpu_max_get_packey(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ const uint64_t *bit = opaque;
+ bool enabled = (cpu->env.cp15.sctlr_el[1] & *bit) != 0;
+
+ visit_type_bool(v, name, &enabled, errp);
+}
+
+static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ Error *err = NULL;
+ const uint64_t *bit = opaque;
+ bool enabled;
+
+ visit_type_bool(v, name, &enabled, errp);
+
+ if (!err) {
+ if (enabled) {
+ cpu->env.cp15.sctlr_el[1] |= *bit;
+ } else {
+ cpu->env.cp15.sctlr_el[1] &= ~*bit;
+ }
+ }
+ error_propagate(errp, err);
+}
+#endif
+
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
* otherwise, a CPU with as many features enabled as our emulation supports.
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -360,6 +392,34 @@ static void aarch64_max_initfn(Object *obj)
*/
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
+
+ /*
+ * Note that Linux will enable enable all of the keys at once.
+ * But doing it this way will allow experimentation beyond that.
+ */
+ {
+ static const uint64_t apia_bit = SCTLR_EnIA;
+ static const uint64_t apib_bit = SCTLR_EnIB;
+ static const uint64_t apda_bit = SCTLR_EnDA;
+ static const uint64_t apdb_bit = SCTLR_EnDB;
+
+ object_property_add(obj, "apia", "bool", cpu_max_get_packey,
+ cpu_max_set_packey, NULL,
+ (void *)&apia_bit, &error_fatal);
+ object_property_add(obj, "apib", "bool", cpu_max_get_packey,
+ cpu_max_set_packey, NULL,
+ (void *)&apib_bit, &error_fatal);
+ object_property_add(obj, "apda", "bool", cpu_max_get_packey,
+ cpu_max_set_packey, NULL,
+ (void *)&apda_bit, &error_fatal);
+ object_property_add(obj, "apdb", "bool", cpu_max_get_packey,
+ cpu_max_set_packey, NULL,
+ (void *)&apdb_bit, &error_fatal);
+
+ /* Enable all PAC keys by default. */
+ cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB;
+ cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB;
+ }
#endif
cpu->sve_max_vq = ARM_MAX_VQ;
--
2.17.2
next prev parent reply other threads:[~2019-01-08 22:33 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 22:30 [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth Richard Henderson
2019-01-08 22:30 ` [Qemu-devel] [PATCH v3 01/31] target/arm: Add state for the ARMv8.3-PAuth extension Richard Henderson
2019-01-18 13:34 ` Peter Maydell
2019-01-21 10:10 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 02/31] target/arm: Add SCTLR bits through ARMv8.5 Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 03/31] target/arm: Add PAuth active bit to tbflags Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra Richard Henderson
2019-01-08 23:26 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 05/31] target/arm: Add PAuth helpers Richard Henderson
2019-01-08 23:28 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 07/31] target/arm: Rearrange decode in disas_data_proc_1src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 08/31] target/arm: Decode PAuth within disas_data_proc_1src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 09/31] target/arm: Decode PAuth within disas_data_proc_2src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 10/31] target/arm: Move helper_exception_return to helper-a64.c Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 11/31] target/arm: Add new_pc argument to helper_exception_return Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 12/31] target/arm: Rearrange decode in disas_uncond_b_reg Richard Henderson
2019-01-18 11:40 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 13/31] target/arm: Decode PAuth within disas_uncond_b_reg Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 14/31] target/arm: Decode Load/store register (pac) Richard Henderson
2019-01-08 23:34 ` Peter Maydell
2019-01-09 11:01 ` Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 15/31] target/arm: Move cpu_mmu_index out of line Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 17/31] target/arm: Introduce arm_stage1_mmu_idx Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 18/31] target/arm: Create ARMVAParameters and helpers Richard Henderson
2019-01-18 11:42 ` Peter Maydell
2019-01-24 11:54 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 19/31] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Richard Henderson
2019-01-18 11:44 ` Peter Maydell
2019-01-18 11:45 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 20/31] target/arm: Export aa64_va_parameters to internals.h Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 21/31] target/arm: Add aa64_va_parameters_both Richard Henderson
2019-01-18 12:00 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 22/31] target/arm: Decode TBID from TCR Richard Henderson
2019-01-18 12:05 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 23/31] target/arm: Reuse aa64_va_parameters for setting tbflags Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 24/31] target/arm: Implement pauth_strip Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 25/31] target/arm: Implement pauth_auth Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 26/31] target/arm: Implement pauth_addpac Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 27/31] target/arm: Implement pauth_computepac Richard Henderson
2019-01-18 12:09 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 28/31] target/arm: Add PAuth system registers Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 29/31] target/arm: Enable PAuth for -cpu max Richard Henderson
2019-01-08 22:31 ` Richard Henderson [this message]
2019-01-18 12:11 ` [Qemu-devel] [PATCH v3 30/31] target/arm: Enable PAuth for user-only Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 31/31] target/arm: Tidy TBI handling in gen_a64_set_pc Richard Henderson
2019-01-09 4:59 ` [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth no-reply
2019-01-18 13:38 ` Peter Maydell
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