From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v3 31/31] target/arm: Tidy TBI handling in gen_a64_set_pc
Date: Wed, 9 Jan 2019 08:31:29 +1000 [thread overview]
Message-ID: <20190108223129.5570-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org>
We can perform this with fewer operations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
v3: Update for tbii = tbi1:tbi0.
---
target/arm/translate-a64.c | 62 +++++++++++++-------------------------
1 file changed, 21 insertions(+), 41 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ee92533469..c398da9214 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val)
/* Load the PC from a generic TCG variable.
*
* If address tagging is enabled via the TCR TBI bits, then loading
- * an address into the PC will clear out any tag in the it:
+ * an address into the PC will clear out any tag in it:
* + for EL2 and EL3 there is only one TBI bit, and if it is set
* then the address is zero-extended, clearing bits [63:56]
* + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
@@ -280,54 +280,34 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
int tbi = s->tbii;
if (s->current_el <= 1) {
- /* Test if NEITHER or BOTH TBI values are set. If so, no need to
- * examine bit 55 of address, can just generate code.
- * If mixed, then test via generated code
- */
- if (tbi == 3) {
- TCGv_i64 tmp_reg = tcg_temp_new_i64();
- /* Both bits set, sign extension from bit 55 into [63:56] will
- * cover both cases
- */
- tcg_gen_shli_i64(tmp_reg, src, 8);
- tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
- tcg_temp_free_i64(tmp_reg);
- } else if (tbi == 0) {
- /* Neither bit set, just load it as-is */
- tcg_gen_mov_i64(cpu_pc, src);
- } else {
- TCGv_i64 tcg_tmpval = tcg_temp_new_i64();
- TCGv_i64 tcg_bit55 = tcg_temp_new_i64();
- TCGv_i64 tcg_zero = tcg_const_i64(0);
+ if (tbi != 0) {
+ /* Sign-extend from bit 55. */
+ tcg_gen_sextract_i64(cpu_pc, src, 0, 56);
- tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
+ if (tbi != 3) {
+ TCGv_i64 tcg_zero = tcg_const_i64(0);
- if (tbi == 1) {
- /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
- tcg_gen_andi_i64(tcg_tmpval, src,
- 0x00FFFFFFFFFFFFFFull);
- tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero,
- tcg_tmpval, src);
- } else {
- /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
- tcg_gen_ori_i64(tcg_tmpval, src,
- 0xFF00000000000000ull);
- tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero,
- tcg_tmpval, src);
+ /*
+ * The two TBI bits differ.
+ * If tbi0, then !tbi1: only use the extension if positive.
+ * if !tbi0, then tbi1: only use the extension if negative.
+ */
+ tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT,
+ cpu_pc, cpu_pc, tcg_zero, cpu_pc, src);
+ tcg_temp_free_i64(tcg_zero);
}
- tcg_temp_free_i64(tcg_zero);
- tcg_temp_free_i64(tcg_bit55);
- tcg_temp_free_i64(tcg_tmpval);
+ return;
}
- } else { /* EL > 1 */
+ } else {
if (tbi != 0) {
/* Force tag byte to all zero */
- tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
- } else {
- /* Load unmodified address */
- tcg_gen_mov_i64(cpu_pc, src);
+ tcg_gen_extract_i64(cpu_pc, src, 0, 56);
+ return;
}
}
+
+ /* Load unmodified address */
+ tcg_gen_mov_i64(cpu_pc, src);
}
typedef struct DisasCompare64 {
--
2.17.2
next prev parent reply other threads:[~2019-01-08 22:33 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 22:30 [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth Richard Henderson
2019-01-08 22:30 ` [Qemu-devel] [PATCH v3 01/31] target/arm: Add state for the ARMv8.3-PAuth extension Richard Henderson
2019-01-18 13:34 ` Peter Maydell
2019-01-21 10:10 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 02/31] target/arm: Add SCTLR bits through ARMv8.5 Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 03/31] target/arm: Add PAuth active bit to tbflags Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra Richard Henderson
2019-01-08 23:26 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 05/31] target/arm: Add PAuth helpers Richard Henderson
2019-01-08 23:28 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 07/31] target/arm: Rearrange decode in disas_data_proc_1src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 08/31] target/arm: Decode PAuth within disas_data_proc_1src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 09/31] target/arm: Decode PAuth within disas_data_proc_2src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 10/31] target/arm: Move helper_exception_return to helper-a64.c Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 11/31] target/arm: Add new_pc argument to helper_exception_return Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 12/31] target/arm: Rearrange decode in disas_uncond_b_reg Richard Henderson
2019-01-18 11:40 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 13/31] target/arm: Decode PAuth within disas_uncond_b_reg Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 14/31] target/arm: Decode Load/store register (pac) Richard Henderson
2019-01-08 23:34 ` Peter Maydell
2019-01-09 11:01 ` Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 15/31] target/arm: Move cpu_mmu_index out of line Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 17/31] target/arm: Introduce arm_stage1_mmu_idx Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 18/31] target/arm: Create ARMVAParameters and helpers Richard Henderson
2019-01-18 11:42 ` Peter Maydell
2019-01-24 11:54 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 19/31] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Richard Henderson
2019-01-18 11:44 ` Peter Maydell
2019-01-18 11:45 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 20/31] target/arm: Export aa64_va_parameters to internals.h Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 21/31] target/arm: Add aa64_va_parameters_both Richard Henderson
2019-01-18 12:00 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 22/31] target/arm: Decode TBID from TCR Richard Henderson
2019-01-18 12:05 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 23/31] target/arm: Reuse aa64_va_parameters for setting tbflags Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 24/31] target/arm: Implement pauth_strip Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 25/31] target/arm: Implement pauth_auth Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 26/31] target/arm: Implement pauth_addpac Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 27/31] target/arm: Implement pauth_computepac Richard Henderson
2019-01-18 12:09 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 28/31] target/arm: Add PAuth system registers Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 29/31] target/arm: Enable PAuth for -cpu max Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 30/31] target/arm: Enable PAuth for user-only Richard Henderson
2019-01-18 12:11 ` Peter Maydell
2019-01-08 22:31 ` Richard Henderson [this message]
2019-01-09 4:59 ` [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth no-reply
2019-01-18 13:38 ` Peter Maydell
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