From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v3 03/31] target/arm: Add PAuth active bit to tbflags
Date: Wed, 9 Jan 2019 08:31:01 +1000 [thread overview]
Message-ID: <20190108223129.5570-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org>
There are 5 bits of state that could be added, but to save
space within tbflags, add only a single enable bit.
Helpers will determine the rest of the state at runtime.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
v2: Fix whitespace, comment grammar.
v3: Rebase on FIELD definition.
---
target/arm/cpu.h | 1 +
target/arm/translate.h | 2 ++
target/arm/helper.c | 19 +++++++++++++++++++
target/arm/translate-a64.c | 1 +
4 files changed, 23 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 843d5936ea..9ad7b2d11e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3014,6 +3014,7 @@ FIELD(TBFLAG_A64, TBI0, 0, 1)
FIELD(TBFLAG_A64, TBI1, 1, 1)
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
+FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
static inline bool bswap_code(bool sctlr_b)
{
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 1550aa8bc7..d8a8bb4e9c 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -68,6 +68,8 @@ typedef struct DisasContext {
bool is_ldex;
/* True if a single-step exception will be taken to the current EL */
bool ss_same_el;
+ /* True if v8.3-PAuth is active. */
+ bool pauth_active;
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
int c15_cpar;
/* TCG op of the current insn_start. */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f00c141ef9..f23555b1dc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12983,6 +12983,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
}
+
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
+ /*
+ * In order to save space in flags, we record only whether
+ * pauth is "inactive", meaning all insns are implemented as
+ * a nop, or "active" when some action must be performed.
+ * The decision of which action to take is left to a helper.
+ */
+ uint64_t sctlr;
+ if (current_el == 0) {
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
+ sctlr = env->cp15.sctlr_el[1];
+ } else {
+ sctlr = env->cp15.sctlr_el[current_el];
+ }
+ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
+ flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
+ }
+ }
} else {
*pc = env->regs[15];
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b7b6ab6371..37a57af715 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -13409,6 +13409,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
+ dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;
--
2.17.2
next prev parent reply other threads:[~2019-01-08 22:31 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 22:30 [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth Richard Henderson
2019-01-08 22:30 ` [Qemu-devel] [PATCH v3 01/31] target/arm: Add state for the ARMv8.3-PAuth extension Richard Henderson
2019-01-18 13:34 ` Peter Maydell
2019-01-21 10:10 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 02/31] target/arm: Add SCTLR bits through ARMv8.5 Richard Henderson
2019-01-08 22:31 ` Richard Henderson [this message]
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra Richard Henderson
2019-01-08 23:26 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 05/31] target/arm: Add PAuth helpers Richard Henderson
2019-01-08 23:28 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 07/31] target/arm: Rearrange decode in disas_data_proc_1src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 08/31] target/arm: Decode PAuth within disas_data_proc_1src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 09/31] target/arm: Decode PAuth within disas_data_proc_2src Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 10/31] target/arm: Move helper_exception_return to helper-a64.c Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 11/31] target/arm: Add new_pc argument to helper_exception_return Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 12/31] target/arm: Rearrange decode in disas_uncond_b_reg Richard Henderson
2019-01-18 11:40 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 13/31] target/arm: Decode PAuth within disas_uncond_b_reg Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 14/31] target/arm: Decode Load/store register (pac) Richard Henderson
2019-01-08 23:34 ` Peter Maydell
2019-01-09 11:01 ` Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 15/31] target/arm: Move cpu_mmu_index out of line Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 17/31] target/arm: Introduce arm_stage1_mmu_idx Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 18/31] target/arm: Create ARMVAParameters and helpers Richard Henderson
2019-01-18 11:42 ` Peter Maydell
2019-01-24 11:54 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 19/31] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Richard Henderson
2019-01-18 11:44 ` Peter Maydell
2019-01-18 11:45 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 20/31] target/arm: Export aa64_va_parameters to internals.h Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 21/31] target/arm: Add aa64_va_parameters_both Richard Henderson
2019-01-18 12:00 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 22/31] target/arm: Decode TBID from TCR Richard Henderson
2019-01-18 12:05 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 23/31] target/arm: Reuse aa64_va_parameters for setting tbflags Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 24/31] target/arm: Implement pauth_strip Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 25/31] target/arm: Implement pauth_auth Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 26/31] target/arm: Implement pauth_addpac Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 27/31] target/arm: Implement pauth_computepac Richard Henderson
2019-01-18 12:09 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 28/31] target/arm: Add PAuth system registers Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 29/31] target/arm: Enable PAuth for -cpu max Richard Henderson
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 30/31] target/arm: Enable PAuth for user-only Richard Henderson
2019-01-18 12:11 ` Peter Maydell
2019-01-08 22:31 ` [Qemu-devel] [PATCH v3 31/31] target/arm: Tidy TBI handling in gen_a64_set_pc Richard Henderson
2019-01-09 4:59 ` [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth no-reply
2019-01-18 13:38 ` Peter Maydell
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