From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: groug@kaod.org, clg@kaod.org, qemu-devel@nongnu.org,
qemu-ppc@nongnu.org,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Richard Henderson <richard.henderson@linaro.org>,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 13/29] target/ppc: replace AVR* macros with Vsr* macros
Date: Wed, 9 Jan 2019 09:45:44 +1100 [thread overview]
Message-ID: <20190108224600.23125-14-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20190108224600.23125-1-david@gibson.dropbear.id.au>
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Now that the VMX and VSR register sets have been combined, the same macros can
be used to access both AVR and VSR field members.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/int_helper.c | 30 +++++++++++++-----------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 9d715be25c..598731d47a 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -391,13 +391,9 @@ target_ulong helper_602_mfrom(target_ulong arg)
#if defined(HOST_WORDS_BIGENDIAN)
#define HI_IDX 0
#define LO_IDX 1
-#define AVRB(i) u8[i]
-#define AVRW(i) u32[i]
#else
#define HI_IDX 1
#define LO_IDX 0
-#define AVRB(i) u8[15-(i)]
-#define AVRW(i) u32[3-(i)]
#endif
#if defined(HOST_WORDS_BIGENDIAN)
@@ -3277,11 +3273,11 @@ void helper_vcipher(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
int i;
VECTOR_FOR_INORDER_I(i, u32) {
- result.AVRW(i) = b->AVRW(i) ^
- (AES_Te0[a->AVRB(AES_shifts[4*i + 0])] ^
- AES_Te1[a->AVRB(AES_shifts[4*i + 1])] ^
- AES_Te2[a->AVRB(AES_shifts[4*i + 2])] ^
- AES_Te3[a->AVRB(AES_shifts[4*i + 3])]);
+ result.VsrW(i) = b->VsrW(i) ^
+ (AES_Te0[a->VsrB(AES_shifts[4 * i + 0])] ^
+ AES_Te1[a->VsrB(AES_shifts[4 * i + 1])] ^
+ AES_Te2[a->VsrB(AES_shifts[4 * i + 2])] ^
+ AES_Te3[a->VsrB(AES_shifts[4 * i + 3])]);
}
*r = result;
}
@@ -3292,7 +3288,7 @@ void helper_vcipherlast(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
int i;
VECTOR_FOR_INORDER_I(i, u8) {
- result.AVRB(i) = b->AVRB(i) ^ (AES_sbox[a->AVRB(AES_shifts[i])]);
+ result.VsrB(i) = b->VsrB(i) ^ (AES_sbox[a->VsrB(AES_shifts[i])]);
}
*r = result;
}
@@ -3305,15 +3301,15 @@ void helper_vncipher(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
ppc_avr_t tmp;
VECTOR_FOR_INORDER_I(i, u8) {
- tmp.AVRB(i) = b->AVRB(i) ^ AES_isbox[a->AVRB(AES_ishifts[i])];
+ tmp.VsrB(i) = b->VsrB(i) ^ AES_isbox[a->VsrB(AES_ishifts[i])];
}
VECTOR_FOR_INORDER_I(i, u32) {
- r->AVRW(i) =
- AES_imc[tmp.AVRB(4*i + 0)][0] ^
- AES_imc[tmp.AVRB(4*i + 1)][1] ^
- AES_imc[tmp.AVRB(4*i + 2)][2] ^
- AES_imc[tmp.AVRB(4*i + 3)][3];
+ r->VsrW(i) =
+ AES_imc[tmp.VsrB(4 * i + 0)][0] ^
+ AES_imc[tmp.VsrB(4 * i + 1)][1] ^
+ AES_imc[tmp.VsrB(4 * i + 2)][2] ^
+ AES_imc[tmp.VsrB(4 * i + 3)][3];
}
}
@@ -3323,7 +3319,7 @@ void helper_vncipherlast(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
int i;
VECTOR_FOR_INORDER_I(i, u8) {
- result.AVRB(i) = b->AVRB(i) ^ (AES_isbox[a->AVRB(AES_ishifts[i])]);
+ result.VsrB(i) = b->VsrB(i) ^ (AES_isbox[a->VsrB(AES_ishifts[i])]);
}
*r = result;
}
--
2.20.1
next prev parent reply other threads:[~2019-01-08 22:46 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 22:45 [Qemu-devel] [PULL 00/29] ppc-for-4.0 queue 20190109 David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 01/29] spapr: Add H-Call H_HOME_NODE_ASSOCIATIVITY David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 02/29] ppc/spapr: Receive and store device tree blob from SLOF David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 03/29] ppc4xx: Disable debug logging by default David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 04/29] MAINTAINERS: Add more files to sam460ex David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 05/29] target/ppc: fix typo in SIMM5 extraction helper David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 06/29] target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32 David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 07/29] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 08/29] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX " David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 09/29] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR " David Gibson
2019-06-04 21:23 ` [Qemu-devel] [Qemu-ppc] " Laurent Vivier
2019-06-05 6:32 ` Mark Cave-Ayland
2019-06-05 7:43 ` Laurent Vivier
2019-06-05 7:47 ` Mark Cave-Ayland
2019-06-06 19:24 ` Laurent Vivier
2019-06-06 20:21 ` Mark Cave-Ayland
2019-06-07 9:19 ` Laurent Vivier
2019-01-08 22:45 ` [Qemu-devel] [PULL 10/29] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 11/29] target/ppc: merge ppc_vsr_t and ppc_avr_t union types David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 12/29] target/ppc: move FP and VMX registers into aligned vsr register array David Gibson
2020-01-24 13:21 ` Peter Maydell
2019-01-08 22:45 ` David Gibson [this message]
2019-01-08 22:45 ` [Qemu-devel] [PULL 14/29] MAINTAINERS: Add some missing ppc-related files David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 15/29] MAINTAINERS: add qemu_vga.ndrv file entry for Mac machines David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 16/29] spapr: move spapr_create_phb() to core machine code David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 17/29] pci: allow cleanup/unregistration of PCI root buses David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 18/29] spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 19/29] spapr/xive: simplify the sPAPR IRQ qirq method for XIVE David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 20/29] spapr: modify the prototype of the cpu_intc_create() method David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 21/29] ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 22/29] ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 23/29] spapr: return from post_load method when RTC import fails David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 24/29] ppc: export the XICS and XIVE set_irq handlers David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 25/29] pnv/psi: move the ICSState qemu_irq array under the PSI device model David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 26/29] spapr: move the qemu_irq array under the machine David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 27/29] ppc/xics: allow ICSState to have an offset 0 David Gibson
2019-01-08 22:45 ` [Qemu-devel] [PULL 28/29] spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS David Gibson
2019-01-08 22:46 ` [Qemu-devel] [PULL 29/29] spapr: enable XIVE MMIOs at reset David Gibson
2019-01-09 23:33 ` [Qemu-devel] [PULL 00/29] ppc-for-4.0 queue 20190109 Peter Maydell
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