From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 11/11] tests/tcg/aarch64: Add bti smoke test
Date: Thu, 10 Jan 2019 23:17:36 +1100 [thread overview]
Message-ID: <20190110121736.23448-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/aarch64/bti-1.c | 61 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 7 +++-
3 files changed, 118 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/aarch64/bti-1.c
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c
new file mode 100644
index 0000000000..fa8a521a47
--- /dev/null
+++ b/tests/tcg/aarch64/bti-1.c
@@ -0,0 +1,61 @@
+/*
+ * Branch target identification, basic notskip cases.
+ */
+
+#include "bti-crt.inc.c"
+
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
+{
+ uc->uc_mcontext.pc += 8;
+}
+
+#define NOP "nop"
+#define BTI_N "hint #32"
+#define BTI_C "hint #34"
+#define BTI_J "hint #36"
+#define BTI_JC "hint #38"
+
+#define BTYPE_1(DEST) \
+ asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
+ : "=r"(skipped) : : "x16")
+
+#define BTYPE_2(DEST) \
+ asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
+ : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_3(DEST) \
+ asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
+ : "=r"(skipped) : : "x15")
+
+#define TEST(WHICH, DEST, EXPECT) \
+ do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0)
+
+
+int main()
+{
+ int fail = 0;
+ int skipped;
+
+ /* Signal-like with SA_SIGINFO. */
+ signal_info(SIGILL, skip2_sigill);
+
+ TEST(BTYPE_1, NOP, 1);
+ TEST(BTYPE_1, BTI_N, 1);
+ TEST(BTYPE_1, BTI_C, 0);
+ TEST(BTYPE_1, BTI_J, 0);
+ TEST(BTYPE_1, BTI_JC, 0);
+
+ TEST(BTYPE_2, NOP, 1);
+ TEST(BTYPE_2, BTI_N, 1);
+ TEST(BTYPE_2, BTI_C, 0);
+ TEST(BTYPE_2, BTI_J, 1);
+ TEST(BTYPE_2, BTI_JC, 0);
+
+ TEST(BTYPE_3, NOP, 1);
+ TEST(BTYPE_3, BTI_N, 1);
+ TEST(BTYPE_3, BTI_C, 1);
+ TEST(BTYPE_3, BTI_J, 0);
+ TEST(BTYPE_3, BTI_JC, 0);
+
+ return fail;
+}
diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c
new file mode 100644
index 0000000000..ef7831ad76
--- /dev/null
+++ b/tests/tcg/aarch64/bti-crt.inc.c
@@ -0,0 +1,51 @@
+/*
+ * Minimal user-environment for testing BTI.
+ *
+ * Normal libc is not built with BTI support enabled, and so could
+ * generate a BTI TRAP before ever reaching main.
+ */
+
+#include <stdlib.h>
+#include <signal.h>
+#include <ucontext.h>
+#include <asm/unistd.h>
+
+int main(void);
+
+void _start(void)
+{
+ exit(main());
+}
+
+void exit(int ret)
+{
+ register int x0 __asm__("x0") = ret;
+ register int x8 __asm__("x8") = __NR_exit;
+
+ asm volatile("svc #0" : : "r"(x0), "r"(x8));
+ __builtin_unreachable();
+}
+
+/*
+ * Irritatingly, the user API struct sigaction does not match the
+ * kernel API struct sigaction. So for simplicity, isolate the
+ * kernel ABI here, and make this act like signal.
+ */
+void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *))
+{
+ struct kernel_sigaction {
+ void (*handler)(int, siginfo_t *, ucontext_t *);
+ unsigned long flags;
+ unsigned long restorer;
+ unsigned long mask;
+ } sa = { fn, SA_SIGINFO, 0, 0 };
+
+ register int x0 __asm__("x0") = sig;
+ register void *x1 __asm__("x1") = &sa;
+ register void *x2 __asm__("x2") = 0;
+ register int x3 __asm__("x3") = sizeof(unsigned long);
+ register int x8 __asm__("x8") = __NR_rt_sigaction;
+
+ asm volatile("svc #0"
+ : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory");
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 08c45b8470..3d56e7c6ea 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -8,10 +8,15 @@ VPATH += $(AARCH64_SRC)
# we don't build any of the ARM tests
AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS))
AARCH64_TESTS+=fcvt
-TESTS:=$(AARCH64_TESTS)
fcvt: LDFLAGS+=-lm
run-fcvt: fcvt
$(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
$(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref)
+
+AARCH64_TESTS += bti-1
+bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib
+run-bti-1: QEMU += -cpu max,guarded_pages=on
+
+TESTS:=$(AARCH64_TESTS)
--
2.17.2
next prev parent reply other threads:[~2019-01-10 12:18 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-10 12:17 [Qemu-devel] [PATCH 00/11] target/arm: Implement ARMv8.5-BTI Richard Henderson
2019-01-10 12:17 ` [Qemu-devel] [PATCH 01/11] target/arm: Introduce isar_feature_aa64_bti Richard Henderson
2019-01-22 12:01 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 02/11] target/arm: Add PSTATE.BTYPE Richard Henderson
2019-01-22 12:08 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 03/11] target/arm: Add BT and BTYPE to tb->flags Richard Henderson
2019-01-22 12:57 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 04/11] target/arm: Record the GP bit for a page in MemTxAttrs Richard Henderson
2019-01-22 13:26 ` Peter Maydell
2019-01-28 21:08 ` Richard Henderson
2019-01-29 9:55 ` Peter Maydell
2019-01-29 14:38 ` Richard Henderson
2019-01-10 12:17 ` [Qemu-devel] [PATCH 05/11] target/arm: Default handling of BTYPE during translation Richard Henderson
2019-01-22 13:50 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 06/11] target/arm: Reset btype for direct branches and syscalls Richard Henderson
2019-01-22 14:12 ` Peter Maydell
2019-01-28 21:28 ` Richard Henderson
2019-01-29 9:57 ` Peter Maydell
2019-01-29 14:05 ` Richard Henderson
2019-01-29 14:06 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 07/11] target/arm: Set btype for indirect branches Richard Henderson
2019-01-22 15:28 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 08/11] target/arm: Add guarded_pages cpu property for user-only Richard Henderson
2019-01-22 15:29 ` Peter Maydell
2019-01-22 15:42 ` Richard Henderson
2019-01-22 16:57 ` Peter Maydell
2019-01-28 22:01 ` Richard Henderson
2019-01-10 12:17 ` [Qemu-devel] [PATCH 09/11] target/arm: Enable BTI for -cpu max Richard Henderson
2019-01-22 15:30 ` Peter Maydell
2019-01-10 12:17 ` [Qemu-devel] [PATCH 10/11] linux-user/aarch64: Reset btype for signal handlers Richard Henderson
2019-01-22 15:46 ` Peter Maydell
2019-01-10 12:17 ` Richard Henderson [this message]
2019-01-31 18:05 ` [Qemu-devel] [PATCH 00/11] target/arm: Implement ARMv8.5-BTI no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190110121736.23448-12-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).