From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH 05/17] target/arm: Suppress tag check for sp+offset
Date: Mon, 14 Jan 2019 12:11:10 +1100 [thread overview]
Message-ID: <20190114011122.5995-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org>
R0078 specifies that base register, or base register plus immediate
offset, is unchecked when the base register is SP.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 5c2577a9ac..ee95ba7165 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -336,12 +336,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
* This is always a fresh temporary, as we need to be able to
* increment this independently of a dirty write-back address.
*/
-static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
+static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool sp_off)
{
TCGv_i64 clean = new_tmp_a64(s);
- /* FIXME: SP+OFS is always unchecked. */
- if (s->tbid && s->mte_active) {
+ if (s->tbid && s->mte_active && !sp_off) {
gen_helper_mte_check(clean, cpu_env, addr);
} else {
gen_top_byte_ignore(s, clean, addr, s->tbid);
@@ -2374,7 +2373,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt,
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx,
size | MO_ALIGN | s->be_data);
}
@@ -2392,7 +2391,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
if (size == 2) {
TCGv_i64 cmp = tcg_temp_new_i64();
@@ -2517,7 +2516,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (is_lasr) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false);
return;
@@ -2526,7 +2525,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, clean_addr, size, false);
if (is_lasr) {
@@ -2546,7 +2545,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
gen_check_sp_alignment(s);
}
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
return;
@@ -2562,7 +2561,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -2576,7 +2575,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (is_lasr) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true);
return;
}
@@ -2594,7 +2593,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, clean_addr, size, true);
if (is_lasr) {
@@ -2784,7 +2783,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
if (!postindex) {
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
}
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
if (is_vector) {
if (is_load) {
@@ -2922,7 +2921,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
if (!post_index) {
tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9);
}
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
if (is_vector) {
if (is_store) {
@@ -3029,7 +3028,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, false);
if (is_vector) {
if (is_store) {
@@ -3114,7 +3113,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
dirty_addr = read_cpu_reg_sp(s, rn, 1);
offset = imm12 << size;
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
if (is_vector) {
if (is_store) {
@@ -3198,7 +3197,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31);
tcg_rs = read_cpu_reg(s, rs, true);
if (o3_opc == 1) { /* LDCLR */
@@ -3259,7 +3258,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
/* Note that "clean" and "dirty" here refer to TBI not PAC. */
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
tcg_rt = cpu_reg(s, rt);
do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false,
@@ -3413,7 +3412,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
elements = (is_q ? 16 : 8) / ebytes;
tcg_rn = cpu_reg_sp(s, rn);
- clean_addr = clean_data_tbi(s, tcg_rn);
+ clean_addr = clean_data_tbi(s, tcg_rn, rn == 31);
tcg_ebytes = tcg_const_i64(ebytes);
for (r = 0; r < rpt; r++) {
@@ -3547,7 +3546,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
}
tcg_rn = cpu_reg_sp(s, rn);
- clean_addr = clean_data_tbi(s, tcg_rn);
+ clean_addr = clean_data_tbi(s, tcg_rn, rn == 31);
tcg_ebytes = tcg_const_i64(ebytes);
for (xs = 0; xs < selem; xs++) {
--
2.17.2
next prev parent reply other threads:[~2019-01-14 1:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-14 1:11 [Qemu-devel] [PATCH 00/17] target/arm: Implement ARMv8.5-MemTag Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-02-05 19:06 ` Peter Maydell
2019-02-10 0:06 ` Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 02/17] target/arm: Extract TCMA with ARMVAParameters Richard Henderson
2019-02-05 19:08 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 03/17] target/arm: Add MTE system registers Richard Henderson
2019-02-05 19:27 ` Peter Maydell
2019-02-10 1:20 ` Richard Henderson
2019-02-10 1:23 ` Richard Henderson
2019-02-10 21:40 ` Peter Maydell
2019-02-10 22:47 ` Richard Henderson
2019-02-11 9:43 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 04/17] target/arm: Fill in helper_mte_check Richard Henderson
2019-02-07 15:57 ` Peter Maydell
2019-01-14 1:11 ` Richard Henderson [this message]
2019-02-07 16:17 ` [Qemu-devel] [PATCH 05/17] target/arm: Suppress tag check for sp+offset Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 06/17] target/arm: Implement the IRG instruction Richard Henderson
2019-02-07 16:47 ` Peter Maydell
2019-02-10 3:43 ` Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-02-07 17:28 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 08/17] target/arm: Implement the GMI instruction Richard Henderson
2019-02-07 17:32 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 09/17] target/arm: Implement the SUBP instruction Richard Henderson
2019-02-07 17:38 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 10/17] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-02-07 17:41 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction Richard Henderson
2019-02-07 17:41 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 12/17] target/arm: Implement the LDGV and STGV instructions Richard Henderson
2019-02-07 17:43 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-02-07 17:44 ` Peter Maydell
2019-02-08 17:16 ` Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 14/17] tcg: Introduce target-specific page data for user-only Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 15/17] target/arm: Add allocation tag storage " Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 16/17] target/arm: Enable MTE Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests Richard Henderson
2019-01-14 14:22 ` Alex Bennée
2019-01-14 21:07 ` Richard Henderson
2019-02-05 19:42 ` [Qemu-devel] [PATCH 00/17] target/arm: Implement ARMv8.5-MemTag Peter Maydell
2019-02-07 17:53 ` Peter Maydell
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