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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space
Date: Fri, 18 Jan 2019 14:57:26 +0000	[thread overview]
Message-ID: <20190118145805.6852-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190108223129.5570-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++-----
 1 file changed, 81 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 37a57af7150..b72aea3e974 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t insn,
     }
 
     switch (selector) {
-    case 0: /* NOP */
-        return;
-    case 3: /* WFI */
+    case 0b00000: /* NOP */
+        break;
+    case 0b00011: /* WFI */
         s->base.is_jmp = DISAS_WFI;
-        return;
+        break;
+    case 0b00001: /* YIELD */
         /* When running in MTTCG we don't generate jumps to the yield and
          * WFE helpers as it won't affect the scheduling of other vCPUs.
          * If we wanted to more completely model WFE/SEV so we don't busy
          * spin unnecessarily we would need to do something more involved.
          */
-    case 1: /* YIELD */
         if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
             s->base.is_jmp = DISAS_YIELD;
         }
-        return;
-    case 2: /* WFE */
+        break;
+    case 0b00010: /* WFE */
         if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
             s->base.is_jmp = DISAS_WFE;
         }
-        return;
-    case 4: /* SEV */
-    case 5: /* SEVL */
+        break;
+    case 0b00100: /* SEV */
+    case 0b00101: /* SEVL */
         /* we treat all as NOP at least for now */
-        return;
+        break;
+    case 0b00111: /* XPACLRI */
+        if (s->pauth_active) {
+            gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
+        }
+        break;
+    case 0b01000: /* PACIA1716 */
+        if (s->pauth_active) {
+            gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 0b01010: /* PACIB1716 */
+        if (s->pauth_active) {
+            gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 0b01100: /* AUTIA1716 */
+        if (s->pauth_active) {
+            gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 0b01110: /* AUTIB1716 */
+        if (s->pauth_active) {
+            gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+        }
+        break;
+    case 0b11000: /* PACIAZ */
+        if (s->pauth_active) {
+            gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
+                                new_tmp_a64_zero(s));
+        }
+        break;
+    case 0b11001: /* PACIASP */
+        if (s->pauth_active) {
+            gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
+    case 0b11010: /* PACIBZ */
+        if (s->pauth_active) {
+            gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30],
+                                new_tmp_a64_zero(s));
+        }
+        break;
+    case 0b11011: /* PACIBSP */
+        if (s->pauth_active) {
+            gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
+    case 0b11100: /* AUTIAZ */
+        if (s->pauth_active) {
+            gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30],
+                              new_tmp_a64_zero(s));
+        }
+        break;
+    case 0b11101: /* AUTIASP */
+        if (s->pauth_active) {
+            gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
+    case 0b11110: /* AUTIBZ */
+        if (s->pauth_active) {
+            gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30],
+                              new_tmp_a64_zero(s));
+        }
+        break;
+    case 0b11111: /* AUTIBSP */
+        if (s->pauth_active) {
+            gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+        }
+        break;
     default:
         /* default specified as NOP equivalent */
-        return;
+        break;
     }
 }
 
-- 
2.20.1

  parent reply	other threads:[~2019-01-18 14:58 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-18 14:57 [Qemu-devel] [PULL 00/49] target-arm queue Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 09/49] target/arm: Add PAuth helpers Peter Maydell
2019-01-18 14:57 ` Peter Maydell [this message]
2019-01-18 14:57 ` [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 12/49] target/arm: Decode PAuth within disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac) Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 29/49] target/arm: Implement pauth_auth Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 30/49] target/arm: Implement pauth_addpac Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 32/49] target/arm: Add PAuth system registers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Peter Maydell
2020-08-24 16:33   ` Peter Maydell
2020-08-25 14:41     ` Aaron Lindsay
2020-08-25 14:48     ` [PATCH] target/arm: Count PMU events when MDCR.SPME is set Aaron Lindsay
2020-09-11 14:13       ` Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial() Peter Maydell
2019-01-31 17:48 ` [Qemu-devel] [PULL 00/49] target-arm queue no-reply

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