From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations
Date: Fri, 18 Jan 2019 14:57:54 +0000 [thread overview]
Message-ID: <20190118145805.6852-39-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org>
From: Aaron Lindsay <aaron@os.amperecomputing.com>
Because of the PMU's design, many register accesses have side effects
which are inter-related, meaning that the normal method of saving CP
registers can result in inconsistent state. These side-effects are
largely handled in pmu_op_start/finish functions which can be called
before and after the state is saved/restored. By doing this and adding
raw read/write functions for the affected registers, we avoid
migration-related inconsistencies.
Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 6 ++++--
target/arm/machine.c | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c49e0d70cbb..733cfdc5a0f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1459,11 +1459,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
.type = ARM_CP_IO,
- .readfn = pmccntr_read, .writefn = pmccntr_write, },
+ .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
+ .readfn = pmccntr_read, .writefn = pmccntr_write,
+ .raw_readfn = raw_read, .raw_writefn = raw_write, },
#endif
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
- .writefn = pmccfiltr_write,
+ .writefn = pmccfiltr_write, .raw_writefn = raw_write,
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 7a22ebc2098..b2925496148 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -620,6 +620,10 @@ static int cpu_pre_save(void *opaque)
{
ARMCPU *cpu = opaque;
+ if (!kvm_enabled()) {
+ pmu_op_start(&cpu->env);
+ }
+
if (kvm_enabled()) {
if (!write_kvmstate_to_list(cpu)) {
/* This should never fail */
@@ -641,6 +645,17 @@ static int cpu_pre_save(void *opaque)
return 0;
}
+static int cpu_post_save(void *opaque)
+{
+ ARMCPU *cpu = opaque;
+
+ if (!kvm_enabled()) {
+ pmu_op_finish(&cpu->env);
+ }
+
+ return 0;
+}
+
static int cpu_pre_load(void *opaque)
{
ARMCPU *cpu = opaque;
@@ -653,6 +668,10 @@ static int cpu_pre_load(void *opaque)
*/
env->irq_line_state = UINT32_MAX;
+ if (!kvm_enabled()) {
+ pmu_op_start(&cpu->env);
+ }
+
return 0;
}
@@ -721,6 +740,10 @@ static int cpu_post_load(void *opaque, int version_id)
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+ if (!kvm_enabled()) {
+ pmu_op_finish(&cpu->env);
+ }
+
return 0;
}
@@ -729,6 +752,7 @@ const VMStateDescription vmstate_arm_cpu = {
.version_id = 22,
.minimum_version_id = 22,
.pre_save = cpu_pre_save,
+ .post_save = cpu_post_save,
.pre_load = cpu_pre_load,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
--
2.20.1
next prev parent reply other threads:[~2019-01-18 14:58 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 14:57 [Qemu-devel] [PULL 00/49] target-arm queue Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 09/49] target/arm: Add PAuth helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 12/49] target/arm: Decode PAuth within disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac) Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 29/49] target/arm: Implement pauth_auth Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 30/49] target/arm: Implement pauth_addpac Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 32/49] target/arm: Add PAuth system registers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses Peter Maydell
2019-01-18 14:57 ` Peter Maydell [this message]
2019-01-18 14:57 ` [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Peter Maydell
2020-08-24 16:33 ` Peter Maydell
2020-08-25 14:41 ` Aaron Lindsay
2020-08-25 14:48 ` [PATCH] target/arm: Count PMU events when MDCR.SPME is set Aaron Lindsay
2020-09-11 14:13 ` Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial() Peter Maydell
2019-01-31 17:48 ` [Qemu-devel] [PULL 00/49] target-arm queue no-reply
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