From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:35715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glefN-0000oN-5H for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefM-0002W6-9s for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:25 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:54296) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefL-0002Ue-Ut for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:24 -0500 Received: by mail-wm1-x343.google.com with SMTP id a62so11833785wmh.4 for ; Mon, 21 Jan 2019 10:51:22 -0800 (PST) From: Peter Maydell Date: Mon, 21 Jan 2019 18:50:56 +0000 Message-Id: <20190121185118.18550-2-peter.maydell@linaro.org> In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 01/23] armv7m: Don't assume the NVIC's CPU is CPU 0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: Peter Maydell --- hw/arm/armv7m.c | 6 ++++-- hw/intc/armv7m_nvic.c | 3 +-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index f4446528307..f9aa83d20ef 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp) } } - /* Tell the CPU where the NVIC is; it will fail realize if it doesn't - * have one. + /* + * Tell the CPU where the NVIC is; it will fail realize if it doesn't + * have one. Similarly, tell the NVIC where its CPU is. */ s->cpu->env.nvic = &s->nvic; + s->nvic.cpu = s->cpu; object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err != NULL) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0beefb05d44..790a3d95849 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2274,8 +2274,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) Error *err = NULL; int regionlen; - s->cpu = ARM_CPU(qemu_get_cpu(0)); - + /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); return; -- 2.20.1