qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: [Qemu-devel] [PATCH 08/23] hw/misc/iotkit-secctl: Support 4 internal MPCs
Date: Mon, 21 Jan 2019 18:51:03 +0000	[thread overview]
Message-ID: <20190121185118.18550-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org>

The SSE-200 has 4 banks of SRAM, each with its own internal
Memory Protection Controller. The interrupt status for these
extra MPCs appears in the same security controller SECMPCINTSTATUS
register as the MPC for the IoTKit's single SRAM bank. Enhance the
iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE
variant in use does not have all 4 MPCs then the unused inputs will
simply result in the SECMPCINTSTATUS bits being zero as required.)

The hardcoded constant "1"s in armsse.c indicate the actual number
of SRAM MPCs the IoTKit has, and will be replaced in the following
commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/iotkit-secctl.h | 6 +++---
 hw/arm/armsse.c                 | 6 +++---
 hw/misc/iotkit-secctl.c         | 5 +++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h
index 1a193b306f1..bcb0437be5b 100644
--- a/include/hw/misc/iotkit-secctl.h
+++ b/include/hw/misc/iotkit-secctl.h
@@ -40,8 +40,8 @@
  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
- * Controlling the MPC in the IoTKit:
- *  + named GPIO input mpc_status
+ * Controlling the (up to) 4 MPCs in the IoTKit/SSE:
+ *  + named GPIO inputs mpc_status[0..3]
  * Controlling each of the 16 expansion MPCs which a system using the IoTKit
  * might provide:
  *  + named GPIO inputs mpcexp_status[0..15]
@@ -67,7 +67,7 @@
 #define IOTS_NUM_APB_EXP_PPC 4
 #define IOTS_NUM_AHB_EXP_PPC 4
 #define IOTS_NUM_EXP_MPC 16
-#define IOTS_NUM_MPC 1
+#define IOTS_NUM_MPC 4
 #define IOTS_NUM_EXP_MSC 16
 
 typedef struct IoTKitSecCtl IoTKitSecCtl;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 8554be14128..074c1d3a6cf 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -138,7 +138,7 @@ static void armsse_init(Object *obj)
                             sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ,
                             &error_abort, NULL);
 
-    for (i = 0; i < ARRAY_SIZE(s->mpc_irq_splitter); i++) {
+    for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) {
         char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
         SplitIRQ *splitter = &s->mpc_irq_splitter[i];
 
@@ -363,7 +363,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
 
     /* We must OR together lines from the MPC splitters to go to the NVIC */
     object_property_set_int(OBJECT(&s->mpc_irq_orgate),
-                            IOTS_NUM_EXP_MPC + IOTS_NUM_MPC, "num-lines", &err);
+                            IOTS_NUM_EXP_MPC + 1, "num-lines", &err);
     if (err) {
         error_propagate(errp, err);
         return;
@@ -636,7 +636,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
     }
 
     /* Wire up the splitters for the MPC IRQs */
-    for (i = 0; i < IOTS_NUM_EXP_MPC + IOTS_NUM_MPC; i++) {
+    for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) {
         SplitIRQ *splitter = &s->mpc_irq_splitter[i];
         DeviceState *dev_splitter = DEVICE(splitter);
 
diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c
index 2222b3e147d..537601cd53f 100644
--- a/hw/misc/iotkit-secctl.c
+++ b/hw/misc/iotkit-secctl.c
@@ -600,7 +600,7 @@ static void iotkit_secctl_mpc_status(void *opaque, int n, int level)
 {
     IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
 
-    s->mpcintstatus = deposit32(s->mpcintstatus, 0, 1, !!level);
+    s->mpcintstatus = deposit32(s->mpcintstatus, n, 1, !!level);
 }
 
 static void iotkit_secctl_mpcexp_status(void *opaque, int n, int level)
@@ -686,7 +686,8 @@ static void iotkit_secctl_init(Object *obj)
     qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
     qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1);
 
-    qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 1);
+    qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status",
+                            IOTS_NUM_MPC);
     qdev_init_gpio_in_named(dev, iotkit_secctl_mpcexp_status,
                             "mpcexp_status", IOTS_NUM_EXP_MPC);
 
-- 
2.20.1

  parent reply	other threads:[~2019-01-21 19:08 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-21 18:50 [Qemu-devel] [PATCH 00/23] arm: Implement MPS2 AN521 FPGA image Peter Maydell
2019-01-21 18:50 ` [Qemu-devel] [PATCH 01/23] armv7m: Don't assume the NVIC's CPU is CPU 0 Peter Maydell
2019-01-21 20:26   ` Philippe Mathieu-Daudé
2019-01-23 23:44   ` Richard Henderson
2019-01-21 18:50 ` [Qemu-devel] [PATCH 02/23] armv7m: Make cpu object a child of the armv7m container Peter Maydell
2019-01-21 20:30   ` Philippe Mathieu-Daudé
2019-01-23 23:44   ` Richard Henderson
2019-01-21 18:50 ` [Qemu-devel] [PATCH 03/23] armv7m: Pass through start-powered-off CPU property Peter Maydell
2019-01-23 23:45   ` Richard Henderson
2019-01-21 18:50 ` [Qemu-devel] [PATCH 04/23] hw/arm/iotkit: Rename IoTKit to ARMSSE Peter Maydell
2019-01-21 20:32   ` Philippe Mathieu-Daudé
2019-01-25 23:46   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 05/23] hw/arm/iotkit: Refactor into abstract base class and subclass Peter Maydell
2019-01-22 11:01   ` Philippe Mathieu-Daudé
2019-01-25 23:52   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 06/23] hw/arm/iotkit: Rename 'iotkit' local variables and functions Peter Maydell
2019-01-22 11:02   ` Philippe Mathieu-Daudé
2019-01-25 23:52   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 07/23] hw/arm/iotkit: Rename files to hw/arm/armsse.[ch] Peter Maydell
2019-01-22 11:03   ` Philippe Mathieu-Daudé
2019-01-26  0:01   ` Richard Henderson
2019-01-21 18:51 ` Peter Maydell [this message]
2019-01-26  0:04   ` [Qemu-devel] [PATCH 08/23] hw/misc/iotkit-secctl: Support 4 internal MPCs Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 09/23] hw/arm/armsse: Make number of SRAM banks parameterised Peter Maydell
2019-01-26  0:06   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 10/23] hw/arm/armsse: Make SRAM bank size configurable Peter Maydell
2019-01-26  0:09   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 11/23] hw/arm/armsse: Support dual-CPU configuration Peter Maydell
2019-01-26  0:14   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 12/23] hw/arm/armsse: Give each CPU its own view of memory Peter Maydell
2019-01-26  0:24   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 13/23] hw/arm/armsse: Put each CPU in its own cluster object Peter Maydell
2019-01-26  0:29   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 14/23] iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurable Peter Maydell
2019-01-26  0:32   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 15/23] hw/arm/armsse: Add unimplemented-device stubs for MHUs Peter Maydell
2019-01-26  0:36   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 16/23] hw/arm/armsse: Add unimplemented-device stubs for PPUs Peter Maydell
2019-01-28 16:17   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 17/23] hw/arm/armsse: Add unimplemented-device stub for cache control registers Peter Maydell
2019-01-28 16:24   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 18/23] hw/arm/armsse: Add unimplemented-device stub for CPU local " Peter Maydell
2019-01-28 16:25   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 19/23] hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block Peter Maydell
2019-01-28 16:26   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 20/23] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 Peter Maydell
2019-01-28 16:27   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 21/23] hw/arm/armsse: Add SSE-200 model Peter Maydell
2019-01-28 16:28   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 22/23] hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200 Peter Maydell
2019-01-28 16:31   ` Richard Henderson
2019-01-21 18:51 ` [Qemu-devel] [PATCH 23/23] hw/arm/mps2-tz: Add mps2-an521 model Peter Maydell
2019-01-28 16:33   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190121185118.18550-9-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=patches@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).