From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de,
richard.henderson@linaro.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions
Date: Wed, 23 Jan 2019 10:25:34 +0100 [thread overview]
Message-ID: <20190123092538.8004-32-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de>
These all expand simply to R format instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24 ++++++++++++++
target/riscv/insn16.decode | 15 +++++----
target/riscv/insn_trans/trans_rvc.inc.c | 44 -------------------------
target/riscv/translate.c | 20 ++++++++---
5 files changed, 54 insertions(+), 59 deletions(-)
create mode 100644 target/riscv/insn16-64.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 9c6c109327..990bd89016 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -5,16 +5,18 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
+
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
-target/riscv/decode_insn16.inc.c: \
- $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 \
+ $(decode16-y), "GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
new file mode 100644
index 0000000000..5af2e2b072
--- /dev/null
+++ b/target/riscv/insn16-64.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc64 targets.
+# All of the fields and formats are there.
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+subw 100 1 11 ... 00 ... 01 @cs_2
+addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 0829e3bc59..c7a58d80e5 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -41,6 +41,9 @@
+# Argument sets imported from insn32.decode:
+&r rd rs1 rs2 !extern
+
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
@@ -68,7 +71,7 @@
@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
-@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@@ -107,12 +110,10 @@ c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
c_srai 100 . 01 ... ..... 01 @c_shift
c_andi 100 . 10 ... ..... 01 @c_andi
-c_sub 100 0 11 ... 00 ... 01 @cs_2
-c_xor 100 0 11 ... 01 ... 01 @cs_2
-c_or 100 0 11 ... 10 ... 01 @cs_2
-c_and 100 0 11 ... 11 ... 01 @cs_2
-c_subw 100 1 11 ... 00 ... 01 @cs_2
-c_addw 100 1 11 ... 01 ... 01 @cs_2
+sub 100 0 11 ... 00 ... 01 @cs_2
+xor 100 0 11 ... 01 ... 01 @cs_2
+or 100 0 11 ... 10 ... 01 @cs_2
+and 100 0 11 ... 11 ... 01 @cs_2
c_j 101 ........... 01 @cj
c_beqz 110 ... ... ..... 01 @cb
c_bnez 111 ... ... ..... 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index bcdf64d3b7..639c381edf 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -163,50 +163,6 @@ static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
return trans_andi(ctx, &arg);
}
-static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
-{
- arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_sub(ctx, &arg);
-}
-
-static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
-{
- arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_xor(ctx, &arg);
-}
-
-static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
-{
- arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_or(ctx, &arg);
-}
-
-static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
-{
- arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_and(ctx, &arg);
-}
-
-static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
-{
-#ifdef TARGET_RISCV64
- arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_subw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
-static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
-{
-#ifdef TARGET_RISCV64
- arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_addw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
{
arg_jal arg = { .rd = 0, .imm = a->imm };
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b0251b3518..5079c68b18 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -487,10 +487,25 @@ static int ex_rvc_register(int reg)
return 8 + reg;
}
+/*
+ * Include the auto-generated decoders.
+ * Note that the 16-bit decoder reuses some of the trans_* functions
+ * from the 32-bit decoder, which results in duplicate declarations
+ * of the relevant helpers. Suppress the warning.
+ */
bool decode_insn32(DisasContext *ctx, uint32_t insn);
-/* Include the auto-generated decoder for 32 bit insn */
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+
#include "decode_insn32.inc.c"
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+
+#include "decode_insn16.inc.c"
+
+#pragma GCC diagnostic pop
+
+
static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -595,9 +610,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
-bool decode_insn16(DisasContext *ctx, uint16_t insn);
-/* auto-generated decoder*/
-#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
static void decode_opc(DisasContext *ctx)
--
2.20.1
next prev parent reply other threads:[~2019-01-23 9:43 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-25 22:23 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-25 22:23 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-25 22:25 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-25 22:27 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-25 22:28 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-25 22:29 ` Alistair
2019-01-23 9:25 ` Bastian Koppelmann [this message]
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply
2019-01-31 18:18 ` no-reply
2019-01-31 18:22 ` no-reply
2019-02-12 23:21 ` Palmer Dabbelt
2019-02-13 2:15 ` Palmer Dabbelt
2019-02-13 9:06 ` Bastian Koppelmann
2019-02-13 15:34 ` Palmer Dabbelt
2019-02-14 0:37 ` Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190123092538.8004-32-kbastian@mail.uni-paderborn.de \
--to=kbastian@mail.uni-paderborn.de \
--cc=palmer@sifive.com \
--cc=peer.adelt@hni.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).