Re: [Qemu-devel] [PATCH v10 00/14] More fully implement ARM PMUv3

[Aaron Lindsay OS <aaron@os.amperecomputing.com>]

On Jan 18 14:13, Peter Maydell wrote:
> On Tue, 11 Dec 2018 at 15:20, Aaron Lindsay
> <aaron@os.amperecomputing.com> wrote:
> >
> > The ARM PMU implementation currently contains a basic cycle counter, but
> > it is often useful to gather counts of other events, filter them based
> > on execution mode, and/or be notified on counter overflow. These patches
> > flesh out the implementations of various PMU registers including
> > PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent
> > arbitrary counter types, implement mode filtering, send interrupts on
> > counter overflow, and add instruction, cycle, and software increment
> > events.
> >
> > Since v9 [1] I have made the following changes:
> > * Added a clarifying comment about how the PMU timer's migration is
> >   handled
> > * Added a check against implementing PMCEID[23] if ID_DFR0.PerfMon ==
> >   0xf
> > * Added TRACEFILT to the ID_DFR0 field definitions
> >
> > [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg00805.html
> >
> 
> Richard has made some comments on patch 14; since 1-13 have
> all been reviewed now I'm going to apply those to target-arm.next.

Thanks.

I also apologize - I just uncovered a bug I should've caught sooner, and
sent out a fix to the list as:

	Subject: [PATCH] target/arm: Don't clear supported PMU events when
	initializing PMCEID1

-Aaron