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From: Aaron Lindsay OS <aaron@os.amperecomputing.com>
Date: Thu, 24 Jan 2019 15:53:48 +0000
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Subject: Re: [Qemu-devel] [PATCH v11 1/2] target/arm: Send interrupts on PMU
 counter overflow
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>, Peter Maydell <peter.maydell@linaro.org>, Alistair Francis <alistair.francis@xilinx.com>, Wei Huang <wei@redhat.com>, Peter Crosthwaite <crosthwaite.peter@gmail.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, Michael Spradling <mspradli@codeaurora.org>, Digant Desai <digantd@codeaurora.org>

On Jan 23 15:37, Richard Henderson wrote:
> On 1/23/19 1:32 PM, Aaron Lindsay OS wrote:
> > +        uint64_t overflow_mask =3D env->cp15.c9_pmcr & PMCRLC ? \
> > +                                 INT64_MIN : INT32_MIN;
>=20
> With type promotion, this is the same as writing
>=20
>     ? 0x8000000000000000ull : 0xffffffff80000000ull
>=20
> which is probably not what you were intending.
>
> Perhaps just ? 1ull << 63 : 1ull << 31 is better?

You are correct. I think we changed this to INT32_MIN in an earlier
respin in an attempt at simplification, but I didn't catch the type
promotion issue.

> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks, I'll send out a v12 momentarily.

-Aaron