* [Qemu-devel] [PATCH] target/riscv: fix counter-enable checks in ctr()
@ 2019-01-26 23:02 Xi Wang
2019-01-29 19:48 ` Palmer Dabbelt
0 siblings, 1 reply; 2+ messages in thread
From: Xi Wang @ 2019-01-26 23:02 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Xi Wang, Michael Clark, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren. The current code
ignores mcounteren and checks scounteren only for U-mode access.
Signed-off-by: Xi Wang <xi.wang@gmail.com>
---
target/riscv/csr.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e7e7d16b8..133f2ff7e2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,9 +56,15 @@ static int fs(CPURISCVState *env, int csrno)
static int ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
- env->priv == PRV_S ? env->mcounteren : -1U;
- if (!(ctr_en & (1 << (csrno & 31)))) {
+ uint32_t ctr_en = ~0u;
+
+ if (env->priv < PRV_M) {
+ ctr_en &= env->mcounteren;
+ }
+ if (env->priv < PRV_S) {
+ ctr_en &= env->scounteren;
+ }
+ if (!(ctr_en & (1u << (csrno & 31)))) {
return -1;
}
#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] target/riscv: fix counter-enable checks in ctr()
2019-01-26 23:02 [Qemu-devel] [PATCH] target/riscv: fix counter-enable checks in ctr() Xi Wang
@ 2019-01-29 19:48 ` Palmer Dabbelt
0 siblings, 0 replies; 2+ messages in thread
From: Palmer Dabbelt @ 2019-01-29 19:48 UTC (permalink / raw)
Cc: qemu-devel, qemu-riscv, xi.wang, mjc, Alistair Francis, sagark,
Bastian Koppelmann
On Sat, 26 Jan 2019 15:02:56 PST (-0800), xi.wang@gmail.com wrote:
> Access to a counter in U-mode is permitted only if the corresponding
> bit is set in both mcounteren and scounteren. The current code
> ignores mcounteren and checks scounteren only for U-mode access.
>
> Signed-off-by: Xi Wang <xi.wang@gmail.com>
> ---
> target/riscv/csr.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5e7e7d16b8..133f2ff7e2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -56,9 +56,15 @@ static int fs(CPURISCVState *env, int csrno)
> static int ctr(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> - target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
> - env->priv == PRV_S ? env->mcounteren : -1U;
> - if (!(ctr_en & (1 << (csrno & 31)))) {
> + uint32_t ctr_en = ~0u;
> +
> + if (env->priv < PRV_M) {
> + ctr_en &= env->mcounteren;
> + }
> + if (env->priv < PRV_S) {
> + ctr_en &= env->scounteren;
> + }
> + if (!(ctr_en & (1u << (csrno & 31)))) {
> return -1;
> }
> #endif
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
I'll add this to my next PR.
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