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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 01/26] target/arm: Fix validation of 32-bit address spaces for aa32
Date: Mon, 28 Jan 2019 18:10:22 +0000	[thread overview]
Message-ID: <20190128181047.20781-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

When tsz == 0, aarch32 selects the address space via exclusion,
and there are no "top_bits" remaining that require validation.

Fixes: ba97be9f4a4
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190125184913.5970-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 92666e52085..e24689f7677 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10447,7 +10447,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
     uint64_t ttbr;
     hwaddr descaddr, indexmask, indexmask_grainsize;
     uint32_t tableattrs;
-    target_ulong page_size, top_bits;
+    target_ulong page_size;
     uint32_t attrs;
     int32_t stride;
     int addrsize, inputsize;
@@ -10487,12 +10487,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
      * We determined the region when collecting the parameters, but we
      * have not yet validated that the address is valid for the region.
      * Extract the top bits and verify that they all match select.
+     *
+     * For aa32, if inputsize == addrsize, then we have selected the
+     * region by exclusion in aa32_va_parameters and there is no more
+     * validation to do here.
      */
-    top_bits = sextract64(address, inputsize, addrsize - inputsize);
-    if (-top_bits != param.select || (param.select && !ttbr1_valid)) {
-        /* In the gap between the two regions, this is a Translation fault */
-        fault_type = ARMFault_Translation;
-        goto do_fault;
+    if (inputsize < addrsize) {
+        target_ulong top_bits = sextract64(address, inputsize,
+                                           addrsize - inputsize);
+        if (-top_bits != param.select || (param.select && !ttbr1_valid)) {
+            /* The gap between the two regions is a Translation fault */
+            fault_type = ARMFault_Translation;
+            goto do_fault;
+        }
     }
 
     if (param.using64k) {
-- 
2.20.1

  reply	other threads:[~2019-01-28 18:10 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-28 18:10 [Qemu-devel] [PULL 00/26] target-arm queue Peter Maydell
2019-01-28 18:10 ` Peter Maydell [this message]
2019-01-28 18:10 ` [Qemu-devel] [PULL 02/26] target/arm: v8m: Ensure IDAU is respected if SAU is disabled Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 03/26] gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0 Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 04/26] arm: Stub out NRF51 TWI magnetometer/accelerometer detection Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 05/26] tests/microbit-test: add TWI stub device test Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 06/26] exec.c: Use correct attrs in cpu_memory_rw_debug() Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 07/26] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 08/26] MAINTAINERS: update microbit ARM board files Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 09/26] target/arm: Don't clear supported PMU events when initializing PMCEID1 Peter Maydell
2019-02-14 17:55   ` Peter Maydell
2019-02-19 14:23     ` Aaron Lindsay OS
2019-02-19 14:33       ` Peter Maydell
2019-02-19 14:45         ` Aaron Lindsay OS
2019-01-28 18:10 ` [Qemu-devel] [PULL 10/26] memory: add memory_region_flush_rom_device() Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 11/26] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 12/26] arm: Instantiate NRF51 special NVM's and NVMC Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 13/26] tests/libqtest: Introduce qtest_init_with_serial() Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 14/26] tests/microbit-test: Make test independent of global_qtest Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 15/26] tests/microbit-test: Check nRF51 UART functionality Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 16/26] checkpatch: Don't emit spurious warnings about block comments Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 17/26] xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 18/26] aspeed/smc: fix default read value Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 19/26] aspeed/smc: define registers for all possible CS Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 20/26] aspeed/smc: Add dummy data register Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 21/26] aspeed/smc: snoop SPI transfers to fake dummy cycles Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 22/26] tests/microbit-test: Add tests for nRF51 NVMC Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 23/26] hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 24/26] qom/cpu: Add cluster_index to CPUState Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 25/26] accel/tcg: Add cluster number to TCG TB hash Peter Maydell
2019-01-28 18:10 ` [Qemu-devel] [PULL 26/26] gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index Peter Maydell
2019-02-01 12:51 ` [Qemu-devel] [PULL 00/26] target-arm queue no-reply

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