* [Qemu-devel] [PULL 1/2] i386: Update stepping of Cascadelake-Server
2019-01-28 19:38 [Qemu-devel] [PULL 0/2] x86 queue, 2019-01-28 Eduardo Habkost
@ 2019-01-28 19:38 ` Eduardo Habkost
2019-01-28 19:38 ` [Qemu-devel] [PULL 2/2] i386: Enable NPT and NRIPSAVE for AMD CPUs Eduardo Habkost
2019-01-31 11:20 ` [Qemu-devel] [PULL 0/2] x86 queue, 2019-01-28 Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Eduardo Habkost @ 2019-01-28 19:38 UTC (permalink / raw)
To: Peter Maydell, qemu-devel; +Cc: Paolo Bonzini, Richard Henderson, Tao Xu
From: Tao Xu <tao3.xu@intel.com>
Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20181227024304.12182-2-tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 747548b7aa..94ac9dee3d 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -122,6 +122,7 @@ GlobalProperty pc_compat_3_1[] = {
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
+ { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
};
const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2f5412592d..43df813327 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2503,7 +2503,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
- .stepping = 5,
+ .stepping = 6,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Qemu-devel] [PULL 2/2] i386: Enable NPT and NRIPSAVE for AMD CPUs
2019-01-28 19:38 [Qemu-devel] [PULL 0/2] x86 queue, 2019-01-28 Eduardo Habkost
2019-01-28 19:38 ` [Qemu-devel] [PULL 1/2] i386: Update stepping of Cascadelake-Server Eduardo Habkost
@ 2019-01-28 19:38 ` Eduardo Habkost
2019-01-31 11:20 ` [Qemu-devel] [PULL 0/2] x86 queue, 2019-01-28 Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Eduardo Habkost @ 2019-01-28 19:38 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, Richard Henderson, Vitaly Kuznetsov
From: Vitaly Kuznetsov <vkuznets@redhat.com>
Modern AMD CPUs support NPT and NRIPSAVE features and KVM exposes these
when present. NRIPSAVE apeared somewhere in Opteron_G3 lifetime (e.g.
QuadCore AMD Opteron 2378 has is but QuadCore AMD Opteron HE 2344 doesn't),
NPT was introduced a bit earlier.
Add the FEAT_SVM leaf to Opteron_G4/G5 and EPYC/EPYC-IBPB cpu models.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20190121155051.5628-1-vkuznets@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 8 ++++++++
target/i386/cpu.c | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 94ac9dee3d..1690b1935f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -114,7 +114,15 @@ GlobalProperty pc_compat_3_1[] = {
{ "intel-iommu", "dma-drain", "off" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
+ { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
+ { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
+ { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
+ { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
+ { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
+ { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
+ { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
+ { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
{ "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 43df813327..7483daef58 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2801,6 +2801,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM,
+ .features[FEAT_SVM] =
+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
/* no xsaveopt! */
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 62xx class CPU",
@@ -2831,6 +2833,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM,
+ .features[FEAT_SVM] =
+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
/* no xsaveopt! */
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 63xx class CPU",
@@ -2877,6 +2881,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
+ .features[FEAT_SVM] =
+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
@@ -2925,6 +2931,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
+ .features[FEAT_SVM] =
+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor (with IBPB)",
.cache_info = &epyc_cache_info,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 4+ messages in thread