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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v2 04/12] exec: Add target-specific tlb bits to MemTxAttrs
Date: Mon, 28 Jan 2019 14:31:10 -0800	[thread overview]
Message-ID: <20190128223118.5255-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org>

These bits can be used to cache target-specific data in cputlb
read from the page tables.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/memattrs.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a1642098..d4a3477d71 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,16 @@ typedef struct MemTxAttrs {
     unsigned int user:1;
     /* Requester ID (for MSI for example) */
     unsigned int requester_id:16;
+    /*
+     * The following are target-specific page-table bits.  These are not
+     * related to actual memory transactions at all.  However, this structure
+     * is part of the tlb_fill interface, cached in the cputlb structure,
+     * and has unused bits.  These fields will be read by target-specific
+     * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
+     */
+    unsigned int target_tlb_bit0 : 1;
+    unsigned int target_tlb_bit1 : 1;
+    unsigned int target_tlb_bit2 : 1;
 } MemTxAttrs;
 
 /* Bus masters which don't specify any attributes will get this,
-- 
2.17.2

  parent reply	other threads:[~2019-01-28 22:42 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-28 22:31 [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 01/12] target/arm: Introduce isar_feature_aa64_bti Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 02/12] target/arm: Add PSTATE.BTYPE Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 03/12] target/arm: Add BT and BTYPE to tb->flags Richard Henderson
2019-01-28 22:31 ` Richard Henderson [this message]
2019-02-04 11:40   ` [Qemu-devel] [PATCH v2 04/12] exec: Add target-specific tlb bits to MemTxAttrs Peter Maydell
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 05/12] target/arm: Cache the GP bit for a page in MemTxAttrs Richard Henderson
2019-02-04 11:41   ` Peter Maydell
2019-02-04 11:58     ` Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 06/12] target/arm: Default handling of BTYPE during translation Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 07/12] target/arm: Reset btype for direct branches Richard Henderson
2019-02-04 11:43   ` Peter Maydell
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 08/12] target/arm: Set btype for indirect branches Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 09/12] target/arm: Add x-guarded-pages cpu property for user-only Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 10/12] target/arm: Enable BTI for -cpu max Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 11/12] linux-user/aarch64: Reset btype for syscalls and signals Richard Henderson
2019-02-04 12:02   ` Peter Maydell
2019-02-04 12:06     ` Richard Henderson
2019-01-28 22:31 ` [Qemu-devel] [PATCH v2 12/12] tests/tcg/aarch64: Add bti smoke test Richard Henderson
2019-01-31 18:12 ` [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI no-reply
2019-01-31 18:21 ` no-reply
2019-01-31 18:21 ` no-reply
2019-01-31 18:30 ` no-reply
2019-01-31 18:34 ` no-reply
2019-02-04 13:09 ` Peter Maydell

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