From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:59170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gog1H-0003WX-91 for qemu-devel@nongnu.org; Tue, 29 Jan 2019 21:54:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gog1F-0000t9-CO for qemu-devel@nongnu.org; Tue, 29 Jan 2019 21:54:31 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:33090) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gog1F-0000sg-2q for qemu-devel@nongnu.org; Tue, 29 Jan 2019 21:54:29 -0500 Received: by mail-pf1-x441.google.com with SMTP id c123so10723567pfb.0 for ; Tue, 29 Jan 2019 18:54:28 -0800 (PST) From: Jim Wilson Date: Tue, 29 Jan 2019 18:54:21 -0800 Message-Id: <20190130025421.12487-1-jimw@sifive.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Jim Wilson Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++ gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++ gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++ 4 files changed, 340 insertions(+) create mode 100644 gdb-xml/riscv-32bit-cpu.xml create mode 100644 gdb-xml/riscv-32bit-csr.xml create mode 100644 gdb-xml/riscv-32bit-fpu.xml diff --git a/configure b/configure index b18281c..f30369a 100755 --- a/configure +++ b/configure @@ -7283,6 +7283,7 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" target_compiler=$cross_cc_riscv32 ;; riscv64) diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml new file mode 100644 index 0000000..c02f86c --- /dev/null +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml new file mode 100644 index 0000000..4aea9e6 --- /dev/null +++ b/gdb-xml/riscv-32bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml new file mode 100644 index 0000000..783287d --- /dev/null +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.7.4