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From: Jim Wilson <jimw@sifive.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Jim Wilson <jimw@sifive.com>
Subject: [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros.
Date: Tue, 29 Jan 2019 18:55:59 -0800	[thread overview]
Message-ID: <20190130025559.12696-1-jimw@sifive.com> (raw)
In-Reply-To: <CAFyWVaZ5tQq4eGaZiPBq7172PB_x3JCqV6c2xo=wSJdgbJakKQ@mail.gmail.com>

This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Signed-off-by: Jim Wilson <jimw@sifive.com>
---
 target/riscv/cpu_bits.h | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5439f47..316d500 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -135,16 +135,22 @@
 /* Legacy Counter Setup (priv v1.9.1) */
 #define CSR_MUCOUNTEREN     0x320
 #define CSR_MSCOUNTEREN     0x321
+#define CSR_MHCOUNTEREN     0x322
 
 /* Machine Trap Handling */
 #define CSR_MSCRATCH        0x340
 #define CSR_MEPC            0x341
 #define CSR_MCAUSE          0x342
-#define CSR_MBADADDR        0x343
+#define CSR_MTVAL           0x343
 #define CSR_MIP             0x344
 
+/* Legacy Machine Trap Handling (priv v1.9.1) */
+#define CSR_MBADADDR        0x343
+
 /* Supervisor Trap Setup */
 #define CSR_SSTATUS         0x100
+#define CSR_SEDELEG         0x102
+#define CSR_SIDELEG         0x103
 #define CSR_SIE             0x104
 #define CSR_STVEC           0x105
 #define CSR_SCOUNTEREN      0x106
@@ -153,9 +159,12 @@
 #define CSR_SSCRATCH        0x140
 #define CSR_SEPC            0x141
 #define CSR_SCAUSE          0x142
-#define CSR_SBADADDR        0x143
+#define CSR_STVAL           0x143
 #define CSR_SIP             0x144
 
+/* Legacy Supervisor Trap Handling (priv v1.9.1) */
+#define CSR_SBADADDR        0x143
+
 /* Supervisor Protection and Translation */
 #define CSR_SPTBR           0x180
 #define CSR_SATP            0x180
@@ -282,6 +291,28 @@
 #define CSR_MHPMCOUNTER30H  0xb9e
 #define CSR_MHPMCOUNTER31H  0xb9f
 
+/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
+#define CSR_HSTATUS         0x200
+#define CSR_HEDELEG         0x202
+#define CSR_HIDELEG         0x203
+#define CSR_HIE             0x204
+#define CSR_HTVEC           0x205
+
+/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
+#define CSR_HSCRATCH        0x240
+#define CSR_HEPC            0x241
+#define CSR_HCAUSE          0x242
+#define CSR_HBADADDR        0x243
+#define CSR_HIP             0x244
+
+/* Legacy Machine Protection and Translation (priv v1.9.1) */
+#define CSR_MBASE           0x380
+#define CSR_MBOUND          0x381
+#define CSR_MIBASE          0x382
+#define CSR_MIBOUND         0x383
+#define CSR_MDBASE          0x384
+#define CSR_MDBOUND         0x385
+
 /* mstatus CSR bits */
 #define MSTATUS_UIE         0x00000001
 #define MSTATUS_SIE         0x00000002
-- 
2.7.4

  parent reply	other threads:[~2019-01-30  2:56 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-30  2:49 [Qemu-devel] [PATCH 0/5 v3] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2019-01-30  2:54 ` [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files Jim Wilson
2019-02-06 23:52   ` Alistair Francis
2019-01-30  2:55 ` [Qemu-devel] [PATCH 2/5 v3] RISC-V: Add 64-bit " Jim Wilson
2019-02-06 23:53   ` Alistair Francis
2019-01-30  2:55 ` Jim Wilson [this message]
2019-02-06 23:54   ` [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros Alistair Francis
2019-01-30  2:56 ` [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs Jim Wilson
2019-02-06 23:55   ` Alistair Francis
2019-01-30  2:57 ` [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files Jim Wilson
2019-02-07  0:04   ` Alistair Francis
2019-02-07  2:05     ` Jim Wilson
2019-02-07 12:04       ` Richard Henderson
2019-02-08 18:16       ` Alistair Francis
2019-02-08 19:08         ` Jim Wilson
2019-02-08 19:28           ` Alistair Francis
2019-02-11 18:17             ` Palmer Dabbelt

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